[coreboot] Yet another idea of an SPI flash chip programmer
peter at stuge.se
Tue Dec 23 15:40:13 CET 2008
FENG Yu Ning wrote:
> Any one know about this?
> I think it is very useful for soldered SPI flashes.
Sure thing. Good work finding that! :) I wonder how easy these are to
FENG Yu Ning wrote:
> > Can you specify your speed requirement? What would be acceptable?
> > It's easier to calculate backwards then.
> I do not have an accurate speed specification in my mind. I read in
> the list recently that some programmer can take 7 mins to program a
> chip. I just don't want to wait that long.
I know that 1 second would be ideal, but what would be good enough?
30s? 1min? 2min? 3min?
And for which flash chip size? That is also important, because double
the size will double the time. :) 4Mbit vs. 16Mbit = 4x the time.
> >>  Is the programmer going to meet my requirement?
> > It is an interesting question. USB has significantly more
> > overhead per bit to be banged, but the bus is also much faster.
> > It may actually be much faster.
> Let me try. If I succeed with this idea, I will post its
> performance to the list.
Please do. The 2232 MPSSE mode's maximum SPI clock is 6MHz, but the
problem is with turnaround time between each sequence of bytes that
are read or written. SST25VF040 can e.g. only write two bytes at a
time in AAI mode and will require status to be input before the next
two bytes can be written so will really exercise the USB
communication. Depending on their USB descriptors, which I don't
think fit this use very well, this need for status reads can slow the
process down quite a lot.
Stream reading should be nice and fast however.
> > especially if you first need to download data from a PC somehow.
> > Then you need 128 Mbits of RAM too, and a RAM controller..
> I also came to something similar. I knew I needed storage for
> buffering, easy to operate, and fast. However, going further is not
> so easy. That's why I looked for an IC.
Another option is to download the data to be flashed "just in time"
so that no buffering is needed. But then the PC communication link
needs more care. I think that is easier than adding RAM however.
> Thanks for your information. It helps.
I'm looking forward to hearing more about this. When your programmer
is finished we should look closer at how to make plugins for
More information about the coreboot