[coreboot] r1090 - in coreboot-v3: northbridge/amd/geodelx northbridge/amd/k8 northbridge/intel/i440bxemulation northbridge/intel/i945 southbridge/amd/amd8111 southbridge/amd/amd8132 southbridge/amd/sb600 southbridge/nvidia/mcp55
svn at coreboot.org
svn at coreboot.org
Wed Dec 31 20:46:15 CET 2008
Author: myles
Date: 2008-12-31 20:46:14 +0100 (Wed, 31 Dec 2008)
New Revision: 1090
Modified:
coreboot-v3/northbridge/amd/geodelx/geodelx.c
coreboot-v3/northbridge/amd/k8/domain.c
coreboot-v3/northbridge/amd/k8/pci.c
coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c
coreboot-v3/northbridge/intel/i945/northbridge.c
coreboot-v3/southbridge/amd/amd8111/lpc.c
coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c
coreboot-v3/southbridge/amd/sb600/lpc.c
coreboot-v3/southbridge/nvidia/mcp55/lpc.c
Log:
specific-resources.diff:
This patch makes specific devices use the updated resource allocation code.
The changes necessary are:
1. Remove all calls to compute_allocate_resources.
2. Don't store resources except in phase4_set_resources.
northbridge/amd/k8/pci.c:
Remove calls to compute_allocate_resource.
Change phase4_assign_resources to phase4_set_resources
southbridge/amd/amd8132/amd8132_bridge.c:
Remove NPUML and NPUMB.
Add a warning for bus disabling.
Remove bridge_{read|set}_resources (they were there for NPUML)
southbridge/nvidia/mcp55/lpc.c:
southbridge/amd/sb600/lpc.c:
Remove references to have_resources.
southbridge/amd/amd8111/lpc.c:
Add resources for subtractive IO and ROM.
northbridge/amd/k8/domain.c:
northbridge/intel/i440bxemulation/i440bx.c:
northbridge/amd/geodelx/geodelx.c:
northbridge/intel/i945/northbridge.c:
northbridge/via/cn700/stage2.c:
Change phase4_assign_resources->phase4_set_resources.
Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-12-31 19:43:34 UTC (rev 1089)
+++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-12-31 19:46:14 UTC (rev 1090)
@@ -111,8 +111,8 @@
for (link = 0; link < dev->links; link++) {
bus = &dev->link[link];
if (bus->children) {
- printk(BIOS_DEBUG, "my_dev_set_resources: phase4_assign_resources %p\n", bus);
- phase4_assign_resources(bus);
+ printk(BIOS_DEBUG, "my_dev_set_resources: phase4_set_resources %p\n", bus);
+ phase4_set_resources(bus);
}
}
@@ -161,7 +161,7 @@
(get_systop(nb_dm) / 1024) - 1024);
}
- phase4_assign_resources(&dev->link[0]);
+ phase4_set_resources(&dev->link[0]);
}
/**
Modified: coreboot-v3/northbridge/amd/k8/domain.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/domain.c 2008-12-31 19:43:34 UTC (rev 1089)
+++ coreboot-v3/northbridge/amd/k8/domain.c 2008-12-31 19:46:14 UTC (rev 1090)
@@ -44,12 +44,8 @@
#include <device/hypertransport.h>
#include <mc146818rtc.h>
#include <lib.h>
-#include <lapic.h>
+#include <lapic.h>
-#ifdef CONFIG_PCI_64BIT_PREF_MEM
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
-#endif
-
#define FX_DEVS 8
extern struct device * __f0_dev[FX_DEVS];
u32 f1_read_config32(unsigned int reg);
@@ -140,24 +136,16 @@
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
- compute_allocate_resource(&dev->link[0], resource,
- IORESOURCE_IO, IORESOURCE_IO);
/* Initialize the system-wide prefetchable memory resource constraints */
resource = new_resource(dev, 1);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
- compute_allocate_resource(&dev->link[0], resource,
- IORESOURCE_MEM | IORESOURCE_PREFETCH,
- IORESOURCE_MEM | IORESOURCE_PREFETCH);
/* Initialize the system-wide memory resource constraints */
resource = new_resource(dev, 2);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
- compute_allocate_resource(&dev->link[0], resource,
- IORESOURCE_MEM | IORESOURCE_PREFETCH,
- IORESOURCE_MEM);
#endif
printk(BIOS_DEBUG, "k8_pci_domain_read_resources done\n");
}
@@ -238,9 +226,6 @@
resource->flags |= IORESOURCE_ASSIGNED;
resource->flags &= ~IORESOURCE_STORED;
#endif
- compute_allocate_resource(&dev->link[0], resource,
- BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
-
resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, "");
@@ -360,7 +345,7 @@
k8_ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
}
- phase4_assign_resources(&dev->link[0]);
+ phase4_set_resources(&dev->link[0]);
}
static unsigned int k8_domain_scan_bus(struct device * dev, unsigned int max)
Modified: coreboot-v3/northbridge/amd/k8/pci.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/pci.c 2008-12-31 19:43:34 UTC (rev 1089)
+++ coreboot-v3/northbridge/amd/k8/pci.c 2008-12-31 19:46:14 UTC (rev 1090)
@@ -355,8 +355,6 @@
resource->gran = log2c(HT_IO_HOST_ALIGN);
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
- compute_allocate_resource(&dev->link[link], resource,
- IORESOURCE_IO, IORESOURCE_IO);
}
/* Initialize the prefetchable memory constraints on the current bus */
@@ -368,9 +366,6 @@
resource->gran = log2c(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
- compute_allocate_resource(&dev->link[link], resource,
- IORESOURCE_MEM | IORESOURCE_PREFETCH,
- IORESOURCE_MEM | IORESOURCE_PREFETCH);
}
/* Initialize the memory constraints on the current bus */
@@ -382,9 +377,6 @@
resource->gran = log2c(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM;
- compute_allocate_resource(&dev->link[link], resource,
- IORESOURCE_MEM | IORESOURCE_PREFETCH,
- IORESOURCE_MEM);
}
}
@@ -441,8 +433,6 @@
if (resource->flags & IORESOURCE_IO) {
u32 base, limit;
- compute_allocate_resource(&dev->link[link], resource,
- IORESOURCE_IO, IORESOURCE_IO);
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
base &= 0xfe000fcc;
@@ -467,11 +457,6 @@
f1_write_config32(reg, base);
} else if (resource->flags & IORESOURCE_MEM) {
u32 base, limit;
- compute_allocate_resource(&dev->link[link], resource,
- IORESOURCE_MEM | IORESOURCE_PREFETCH,
- resource->
- flags & (IORESOURCE_MEM |
- IORESOURCE_PREFETCH));
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
base &= 0x000000f0;
@@ -581,7 +566,7 @@
struct bus *bus;
bus = &dev->link[link];
if (bus->children) {
- phase4_assign_resources(bus);
+ phase4_set_resources(bus);
}
}
}
Modified: coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c
===================================================================
--- coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-12-31 19:43:34 UTC (rev 1089)
+++ coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-12-31 19:46:14 UTC (rev 1090)
@@ -80,7 +80,7 @@
/* 768 kB .. Systop (in KB) */
ram_resource(dev, idx++, 768, tolmk - 768);
}
- phase4_assign_resources(&dev->link[0]);
+ phase4_set_resources(&dev->link[0]);
}
/* Here are the operations for when the northbridge is running a PCI domain. */
Modified: coreboot-v3/northbridge/intel/i945/northbridge.c
===================================================================
--- coreboot-v3/northbridge/intel/i945/northbridge.c 2008-12-31 19:43:34 UTC (rev 1089)
+++ coreboot-v3/northbridge/intel/i945/northbridge.c 2008-12-31 19:46:14 UTC (rev 1090)
@@ -164,7 +164,7 @@
i945_ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
}
- phase4_assign_resources(&dev->link[0]);
+ phase4_set_resources(&dev->link[0]);
}
static unsigned int i945_pci_domain_scan_bus(struct device * dev, unsigned int max)
Modified: coreboot-v3/southbridge/amd/amd8111/lpc.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-12-31 19:43:34 UTC (rev 1089)
+++ coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-12-31 19:46:14 UTC (rev 1090)
@@ -184,11 +184,19 @@
pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O */
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ res = new_resource(dev, 0);
+ res->base = 0x0;
+ res->size = 0x1000;
+ res->limit = 0xffff;
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_STORED;
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ res = new_resource(dev, 1);
+ res->base = 0xff000000UL;
+ res->size = 0x01000000UL;
+ res->limit = 0xffffffffUL;
+ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_STORED;
}
static void amd8111_lpc_enable_resources(struct device * dev)
Modified: coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c 2008-12-31 19:43:34 UTC (rev 1089)
+++ coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c 2008-12-31 19:46:14 UTC (rev 1090)
@@ -31,8 +31,13 @@
#define NMI_OFF 0
-#define NPUML 0xD9 /* Non prefetchable upper memory limit */
-#define NPUMB 0xD8 /* Non prefetchable upper memory base */
+/* We don't implement this because:
+ * 1. There's only one pair of registers for both devices.
+ * - This breaks our model for resource allocation.
+ * 2. The datasheet recommends against it.
+ */
+/* #define NPUML 0xD9 Non prefetchable upper memory limit */
+/* #define NPUMB 0xD8 Non prefetchable upper memory base */
static void amd8132_walk_children(struct bus *bus,
void (*visit)(struct device * dev, void *ptr), void *ptr)
@@ -165,6 +170,7 @@
info.master_devices = 0;
amd8132_walk_children(bus, amd8132_count_dev, &info);
+#warning Bus disabling disabled for amd8132
#if 0
/* Disable the bus if there are no devices on it
*/
@@ -309,40 +315,6 @@
return;
}
-static void bridge_read_resources(struct device *dev)
-{
- struct resource *res;
- pci_bus_read_resources(dev);
- res = probe_resource(dev, PCI_MEMORY_BASE);
- if (res) {
- res->limit = 0xffffffffffULL;
- }
-}
-
-static void bridge_set_resources(struct device *dev)
-{
- struct resource *res;
- res = find_resource(dev, PCI_MEMORY_BASE);
- if (res) {
- resource_t base, end;
- /* set the memory range */
- dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
- res->flags |= IORESOURCE_STORED;
- compute_allocate_resource(&dev->link[0], res,
- IORESOURCE_MEM | IORESOURCE_PREFETCH,
- IORESOURCE_MEM);
- base = res->base;
- end = resource_end(res);
- pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
- pci_write_config8(dev, NPUML, (base >> 32) & 0xff);
- pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
- pci_write_config8(dev, NPUMB, (end >> 32) & 0xff);
-
- report_resource_stored(dev, res, "including NPUML");
- }
- pci_set_resources(dev);
-}
-
struct device_operations amd8132_pcix = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
@@ -350,8 +322,8 @@
.constructor = default_device_constructor,
.reset_bus = pci_bus_reset,
.phase3_scan = amd8132_scan_bridge,
- .phase4_read_resources = bridge_read_resources,
- .phase4_set_resources = bridge_set_resources,
+ .phase4_read_resources = pci_bus_read_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = amd8132_pcix_init,
.ops_pci = &pci_bus_ops_pci,
Modified: coreboot-v3/southbridge/amd/sb600/lpc.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/lpc.c 2008-12-31 19:43:34 UTC (rev 1089)
+++ coreboot-v3/southbridge/amd/sb600/lpc.c 2008-12-31 19:46:14 UTC (rev 1090)
@@ -110,8 +110,7 @@
for (child = dev->link[link].children; child;
child = child->sibling) {
dev_phase5(child);
- if (child->have_resources
- && (child->path.type == DEVICE_PATH_PNP)) {
+ if (child->path.type == DEVICE_PATH_PNP) {
for (i = 0; i < child->resources; i++) {
struct resource *res;
unsigned long base, end; /* don't need long long */
Modified: coreboot-v3/southbridge/nvidia/mcp55/lpc.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-12-31 19:43:34 UTC (rev 1089)
+++ coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-12-31 19:46:14 UTC (rev 1090)
@@ -292,7 +292,7 @@
struct device *child;
for (child = dev->link[link].children; child; child = child->sibling) {
dev_phase5(child);
- if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
+ if(child->path.type == DEVICE_PATH_PNP) {
for(i=0;i<child->resources;i++) {
struct resource *res;
unsigned long base, end; // don't need long long
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