[coreboot] Testing results CN10000, Via chipsets CN700 and VT8237 with a C7 CPU, and a Kingstom DDR2 memory.
Urbez Santana Roma
urbez at linuxupc.upc.edu
Sat Feb 2 17:08:42 CET 2008
With my project RemoteBIOS and one elf portion of coreboot, i have
tested the CN10000 mainboard, with the RAM initialization routines,
written by Corey Osgood, and the code of VT8237R written by Rudolf
I have found the first problem, that i have resolved, the memory
initialization must use the 20 bit
active when use a CBR memory comand:
do_ram_command( RAM_COMMAND_MRS, 0x0022d8);
do_ram_command( RAM_COMMAND_MRS, 0x1022d8);
do_ram_command( RAM_COMMAND_MRS, 0x21c20);
do_ram_command( RAM_COMMAND_MRS, 0x121c20);
do_ram_command( RAM_COMMAND_MRS, 0x20020);
do_ram_command( RAM_COMMAND_MRS, 0x120020);
Without the 20 bit active, the Kingstom Memory not works.
The detection of SPD: The ram returns:
With the last code of corey, the result of configuration for
PCI(0,0,3)[0x40] are 0x08, and is the correct value for the 512MB RAM
that i have.
Be careful, with that, i not use ROMCC for generate the code of the
function sdram_set_spd_registers() written by Corey, i use directly gcc
The code of disable SATA works, but the normal IDE does not apear too,
with the disable_sata() function. If you use the function, SATA and IDE
goes disabled, i have ignored at the moment these function, y must
investigate what happends.
I have generated the fadt and the dsdt with the genfadt and gendsdt and,
ACPI works fine.
I must force the kernel with acpi=force, and enable lapic, changing the
code of the Linux
kernel, that do not support for Centaur Vendors, and then both ACPI and
the LAPIC works.
All IRQ's works good, and the linux works.
What not works? the control of the Memory in the SuperIO, none of the
features, can control
the memory with DMA, for example VIA-Rhine, and VIA VT82xxx IDE. Then i
must in the kernel
write the parameter ide=nodma. And then the Linux works, without DMA,
and without complete
work with the Ethernet, are detected, but fails in the first interrupt.
I are testing more, how to enable the access of the southbrigde to the
memory, for DMA
actions, but i not have documentation, but can test the southbrigde PCI
with relative speed, only changing a script, for test.
I say us, if i have luck.
Thanks all for read this.
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