[coreboot] patch: init gx cache earlier.

[Marc Jones]

ron minnich wrote:

> We're still far too slow, perhaps because we are not caching ROM? 

Correct. Here is a patch that changes that. BUT, here is a problem here. 
Due to some cache coherency snoop problems across pci we need the ROM 
cache properties to be write-serialize + cache disabled.

My suggestion is to reset the ROM cache properties in stage2 once code 
is executing in memory. The problem is that stage2 returns to stage1 to 
load the payload. v3 would be slow again trying to decompress the payload.

I don't have any good ideas to fix this yet. I don't know if any other 
systems will have similar problems with going back to the ROM to load 
payloads. Most BIOS "shadow" and this isn't an issues. It isn't an issue 
in v2 because the payload load code is in memory.


Marc


-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors
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