[coreboot] Run PCI rom before PCI bus scan??
joe at smittys.pointclark.net
joe at smittys.pointclark.net
Fri Feb 8 14:55:50 CET 2008
Quoting Corey Osgood <corey.osgood at gmail.com>:
>> I apologize if this seems disorganized, I'm trying to work it out:
>>
>> 1: set up csr memory/io base in the nic. ami bios uses 0xff7ff000 for mem
>> base, and 0xdc01 as io base, these values should work to test with.
>> Datasheet contradicts itself, says bits 3:0 of the mem base registers are
>> all hardwired to 0, then gives a default value of 0x8.
>>
>> 2: write 0x3 to register 0xe (in IO space?) to enable the rom and clock.
>> if this is io space, the write is just outb(val, (NIC_IO_BASE + reg)). There
>> are reserved registers, so be sure to do a read-modify-write.
>>
>> 3: reset the lan controller? write 1 to bit 3 of 0x1c. Wait 1ms
>> afterwards.
>>
>> Good luck, hope this helps
>>
>>
I think your right Corey, we need to setup space for for the CSR
register first:
Control/Status Register (CSR) Accesses
The integrated LAN controller supports zero wait-state single cycle
memory or I/O mapped accesses to its CSR space. Separate BARs request
4 KB of memory space and 64 bytes of I/O space to accomplish this.
Based on its needs, the software driver will use either memory or I/O
mapping to access these registers. The LAN controller provides four
valid Kbytes of CSR space, which include the following elements:
? System Control Block (SCB) registers ***(I know for a fact this is
part of the pci rom)***
? PORT register
? EEPROM control register
? MDI control register
? Flow control registers
In the case of accessing the Control/Status Registers, the processor
is the initiator and the LAN controller is the target.
Read Accesses: The processor, as the initiator, drives address lines
AD[31:0], the command and byte enable lines C/BE[3:0]# and the control
lines IRDY# and FRAME#. As a slave, the LAN controller controls the
TRDY# signal and provides valid data on each data access. The LAN
controller allows the processor to issue only one read cycle when it
accesses the Control/Status Registers, generating a disconnect by
asserting the STOP# signal. The processor can insert waitstates by
deasserting IRDY# when it is not ready.
Write Accesses: The processor, as the initiator, drives the address
lines AD[31:0], the command and byte enable lines C/BE[3:0]# and the
control lines IRDY# and FRAME#. It also provides the LAN controller
with valid data on each data access immediately after asserting IRDY#.
The LAN controller controls the TRDY# signal and asserts it from the
data access. The LAN controller allows the processor to issue only one
I/O write cycle to the Control/Status Registers, generating a
disconnect by asserting the STOP# signal. This is true for both memory
mapped and I/O mapped accesses.
How to do this???
Thanks - Joe
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