[coreboot] PIRQ tables...
Stefan Reinauer
stepan at coresystems.de
Sat Feb 9 18:27:59 CET 2008
Ron,
one question though:
how does the information in the DTS relate to the information in the
file irq_tables.c below?
Do we have to specify polarity and interrupt enables twice now?
We need to add all information from irq_tables.c to the mainboard DTS
and read it from there. The mainboard DTS is our central data structure.
something like
eth0 { routing = "C, D, A, B"; polarity="level" };
pci_slot1 { routing = "B, C, D, A"; polarity="edge" };
pci_slot2 { ... };
agp_slot { .... };
I know the only truth is sending patches, but I see we're falling back
into an old, overhauled scheme here and we should rethink careful.
Two places for defining things is a 100% guarantee for failures to
happen.
Stefan
* svn at coreboot.org <svn at coreboot.org> [080209 17:33]:
> Modified: coreboot-v3/mainboard/pcengines/alix1c/dts
> ===================================================================
> --- coreboot-v3/mainboard/pcengines/alix1c/dts 2008-02-08 15:57:02 UTC (rev 581)
> +++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-02-09 16:32:59 UTC (rev 582)
> @@ -43,6 +43,16 @@
> pcipath = "0xf,0";
> enabled;
> enable_ide = "1";
> + /* Interrupt enables for LPC bus.
> + * Each bit is an IRQ 0-15. */
> + lpc_serirq_enable = "0x000010da";
> + /* LPC IRQ polarity. Each bit is an IRQ 0-15. */
> + lpc_serirq_polarity = "0x0000EF25";
> + /* 0:continuous 1:quiet */
> + lpc_serirq_mode = "1";
> + /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.
> + * See virtual PIC spec. */
> + enable_gpio_int_route = "0x0D0C0700";
> };
> superio {
> /config/("superio/winbond/w83627hf/dts");
>
> Added: coreboot-v3/mainboard/pcengines/alix1c/irq_tables.c
> ===================================================================
> --- coreboot-v3/mainboard/pcengines/alix1c/irq_tables.c (rev 0)
> +++ coreboot-v3/mainboard/pcengines/alix1c/irq_tables.c 2008-02-09 16:32:59 UTC (rev 582)
> +
> +/* Platform IRQs */
> +#define PIRQA 11
> +#define PIRQB 10
> +#define PIRQC 11
> +#define PIRQD 9
> +
> + * What Device IRQ PIN PIN WIRED TO
> + * -------------------------------------------------
> + * AES 00:01.2 0a 01 A A
> + * 3VPCI 00:0c.0 0a 01 A A
> + * eth0 00:0d.0 0b 01 A B
> + * mpci 00:0e.0 0a 01 A A
> + * usb 00:0f.3 0b 02 B B
> + * usb 00:0f.4 0b 04 D D
> + * usb 00:0f.5 0b 04 D D
> +
> + /* CPU */
> + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
> +
> + /* PCI (slot 1) */
> + {0x00, (0x0C << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x4, 0x0},
> +
> + /* On-board ethernet */
> + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
> +
> + /* Mini PCI (slot 2) */
> + {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},
> +
> + /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
> + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
> + }
> +};
--
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