[coreboot] [PATCH] v3: printk buffer

Marc Jones Marc.Jones at AMD.com
Wed Feb 13 02:48:05 CET 2008



Carl-Daniel Hailfinger wrote:
> Ron? Marc? Can anyone check this on real hardware?
> The printk buffer is located in Geode LX memory:
> - while CAR is enabled: starting at 0x80000 (CONFIG_CARBASE) size 16k
> (CONFIG_CARSIZE / 2)
> - after CAR is disabled: starting at 0x90000 size 64k
>
>   
This works for Geode. There may be problems with doing this with the K8 
or Fam10 code. A lot more of the CAR stack is used for buffers for 
memory training. I think that it would be good to have a setting to 
control the amount of CAR used. It is just half right now. This would 
also fix the case where you can't use CAR buffer but still want console 
buffer from memory init.

This is good stuff.
Acked-by: Marc Jones <marc.jones at amd.com>

Here is the output from my LX system:
dump 0x80000..+16384 ascii

coreboot-3.0.0 Tue Feb 12 18:25:19 MST 2008 starti
00080040ul  ng...
Choosing fallback boot.
LAR: Attempting to open 'fallback/
00080080ul  initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: seen m
000800C0ul  ember normal/payload/segment0
LAR: seen member normal/payload/se
00080100ul  gment1
LAR: seen member normal/payload/segment2
LAR: seen member
00080140ul   normal/option_table
LAR: seen member normal/stage2/segment0
LAR
00080180ul  : seen member normal/stage2/segment1
LAR: seen member normal/sta
000801C0ul  ge2/segment2
LAR: seen member normal/initram/segment0
LAR: seen
00080200ul  member blob/vsa
LAR: seen member bootblock
LAR: File not found!

00080240ul  LAR: Run file fallback/initram/segment0 failed: No such file.
Fa
00080280ul  llback failed. Try normal boot
LAR: Attempting to open 'normal/i
000802C0ul  nitram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: seen me
00080300ul  mber normal/payload/segment0
LAR: seen member normal/payload/seg
00080340ul  ment1
LAR: seen member normal/payload/segment2
LAR: seen member
00080380ul  normal/option_table
LAR: seen member normal/stage2/segment0
LAR:
000803C0ul   seen member normal/stage2/segment1
LAR: seen member normal/stag
00080400ul  e2/segment2
LAR: seen member normal/initram/segment0
LAR: CHECK
00080440ul  normal/initram/segment0 @ 0xfff8cd80
start 0xfff8cdd0 len 5372 r
00080480ul  eallen 5372 compression 0 entry 0x00000f04 loadaddress 0x0000000
000804C0ul  0
Entry point is 0xfff8dcd4
Hi there from stage1
done preinit
do
00080500ul  ne gpio init
pll_reset: read msr 0x4c000014
_MSR GLCP_SYS_RSTPLL
00080540ul   (4c000014) value is: 00000398:07de005e
Done pll_reset
done pll
00080580ul  reset
spd_read_byte dev 00a0
 addr 0d returns 08
spd_read_byte d
000805C0ul  ev 00a0
 addr 05 returns 01
spd_read_byte dev 00a2
 returns 0xff
00080600ul 
Done cpubug fixes
done cpu reg init
done sdram set registers
sp
00080640ul  d_read_byte dev 00a0
 addr 15 returns ff
spd_read_byte dev 00a2

00080680ul   returns 0xff
spd_read_byte dev 00a0
 addr 09 returns 0a
spd_rea
000806C0ul  d_byte dev 00a2
 returns 0xff
========== Check present =========
00080700ul  ==============================================
spd_read_byte dev
00080740ul   00a0
 addr 02 returns 07
========== MODBANKS ==================
00080780ul  ==========================================
spd_read_byte dev 00a
000807C0ul  0
 addr 05 returns 01
========== FIELDBANKS ====================
00080800ul  ======================================
spd_read_byte dev 00a0
 a
00080840ul  ddr 11 returns 04
========== SPDNUMROWS ========================
00080880ul  ==================================
spd_read_byte dev 00a0
 addr
000808C0ul  03 returns 03
spd_read_byte dev 00a0
 addr 04 returns 0a
=======
00080900ul  === SPDBANKDENSITY =============================================
00080940ul  =========
spd_read_byte dev 00a0
 addr 1f returns 40
==========
00080980ul  BEFORT CTZ =====================================================
000809C0ul  =====
========== TEST DIMM SIZE>8 ==============================
00080A00ul  ======================
========== PAGESIZE =====================
00080A40ul  =======================================
spd_read_byte dev 00a0
 
00080A80ul  addr 04 returns 0a
========== MAXCOLADDR =======================
00080AC0ul  ===================================
========== RDMSR CF07 ======
00080B00ul  ====================================================
==========
00080B40ul  WRMSR CF07 =====================================================
00080B80ul  =====
========== ALL DONE ======================================
00080BC0ul  ======================
========== Check present ================
00080C00ul  =======================================
spd_read_byte dev 00a2
 
00080C40ul  returns 0xff
spd_read_byte dev 00a0
 addr 12 returns 10
spd_read
00080C80ul  _byte dev 00a0
 addr 17 returns 3c
spd_read_byte dev 00a0
 addr
00080CC0ul  19 returns 4b
spd_read_byte dev 00a2
 returns 0xff
spd_read_byte
00080D00ul   dev 00a0
 addr 1e returns 28
spd_read_byte dev 00a2
 returns 0x
00080D40ul  ff
spd_read_byte dev 00a0
 addr 1b returns 0f
spd_read_byte dev
00080D80ul  00a2
 returns 0xff
spd_read_byte dev 00a0
 addr 1d returns 0f
sp
00080DC0ul  d_read_byte dev 00a2
 returns 0xff
spd_read_byte dev 00a0
 addr
00080E00ul  1c returns 0a
spd_read_byte dev 00a2
 returns 0xff
spd_read_byte
00080E40ul   dev 00a0
 addr 2a returns 46
spd_read_byte dev 00a2
 returns 0x
00080E80ul  ff
spd_read_byte dev 00a0
 addr 16 returns ff
spd_read_byte dev
00080EC0ul  00a2
 returns 0xff
spd_read_byte dev 00a0
 addr 0c returns 3a
sp
00080F00ul  d_read_byte dev 00a2
 returns 0xff
done sdram set spd registers

00080F40ul  DRAM controller init done.
RAM DLL lock
done sdram enable
stage1
00080F80ul   returns
run_file returns with 0
Done RAM init code
========== D
00080FC0ul  isable_car: done wbinvd ========================================
00081000ul  ====
Enter northbridge_init_early
writeglmsr: MSR 0x10000020, va
00081040ul  l 0x20000000:0x000fff80
writeglmsr: MSR 0x10000021, val 0x200000
00081080ul  00:0x080fffe0
sizeram: _MSR MC_CF07_DATA: 10076013:00040f40
size
000810C0ul  ram: sizem 0x100MB
sysmem_init: enable for 256MBytes
Usable RAM:
00081100ul   268304383 bytes
sysmem_init: MSR 0x10000028, val 0x2000000f:0xf
00081140ul  df00100
sizeram: _MSR MC_CF07_DATA: 10076013:00040f40
sizeram: s
00081180ul  izem 0x100MB
SMMGL0Init: 268304384 bytes
SMMGL0Init: offset is 0
000811C0ul  x80400000
SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0

00081200ul  writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003
writeglmsr
00081240ul  : MSR 0x40000020, val 0x20000000:0x000fff80
writeglmsr: MSR 0x40
00081280ul  000021, val 0x20000000:0x080fffe0
sizeram: _MSR MC_CF07_DATA: 10
000812C0ul  076013:00040f40
sizeram: sizem 0x100MB
sysmem_init: enable for 2
00081300ul  56MBytes
Usable RAM: 268304383 bytes
sysmem_init: MSR 0x4000002a
00081340ul  , val 0x2000000f:0xfdf00100
SMMGL1Init:
SMMGL1Init: MSR 0x400000
00081380ul  23, val 0x20000080:0x400fffe0
writeglmsr: MSR 0x40000080, val 0x
000813C0ul  00000000:0x00000001
writeglmsr: MSR 0x400000e3, val 0x60000000:0
00081400ul  x033000f0
CPU_RCONF_DEFAULT (1808): 0x04FFFC02:0x10FFDF00
CPU_RC
00081440ul  ONF_BYPASS (180A): 0x00000000 : 0x00000000
L2 cache enabled
GLPC
00081480ul  I R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000
GLPCI R2: syste
000814C0ul  m msr.lo 0x80400120 msr.hi 0x8041f000
Exit northbridge_init_earl
00081500ul  y
========== disable_car: done =================================
00081540ul  ==================

...nothing after this point in 0x80000

59> dump 0x90000..+16384 ascii
00090000ul
coreboot-3.0.0 Tue Feb 12 18:25:19 MST 2008 starti
00090040ul  ng...
Choosing fallback boot.
LAR: Attempting to open 'fallback/
00090080ul  initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: seen m
000900C0ul  ember normal/payload/segment0
LAR: seen member normal/payload/se
00090100ul  gment1
LAR: seen member normal/payload/segment2
LAR: seen member
00090140ul   normal/option_table
LAR: seen member normal/stage2/segment0
LAR
00090180ul  : seen member normal/stage2/segment1
LAR: seen member normal/sta
000901C0ul  ge2/segment2
LAR: seen member normal/initram/segment0
LAR: seen
00090200ul  member blob/vsa
LAR: seen member bootblock
LAR: File not found!

00090240ul  LAR: Run file fallback/initram/segment0 failed: No such file.
Fa
00090280ul  llback failed. Try normal boot
LAR: Attempting to open 'normal/i
000902C0ul  nitram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: seen me
00090300ul  mber normal/payload/segment0
LAR: seen member normal/payload/seg
00090340ul  ment1
LAR: seen member normal/payload/segment2
LAR: seen member
00090380ul  normal/option_table
LAR: seen member normal/stage2/segment0
LAR:
000903C0ul   seen member normal/stage2/segment1
LAR: seen member normal/stag
00090400ul  e2/segment2
LAR: seen member normal/initram/segment0
LAR: CHECK
00090440ul  normal/initram/segment0 @ 0xfff8cd80
start 0xfff8cdd0 len 5372 r
00090480ul  eallen 5372 compression 0 entry 0x00000f04 loadaddress 0x0000000
000904C0ul  0
Entry point is 0xfff8dcd4
Hi there from stage1
done preinit
do
00090500ul  ne gpio init
pll_reset: read msr 0x4c000014
_MSR GLCP_SYS_RSTPLL
00090540ul   (4c000014) value is: 00000398:07de005e
Done pll_reset
done pll
00090580ul  reset
spd_read_byte dev 00a0
 addr 0d returns 08
spd_read_byte d
000905C0ul  ev 00a0
 addr 05 returns 01
spd_read_byte dev 00a2
 returns 0xff
00090600ul 
Done cpubug fixes
done cpu reg init
done sdram set registers
sp
00090640ul  d_read_byte dev 00a0
 addr 15 returns ff
spd_read_byte dev 00a2

00090680ul   returns 0xff
spd_read_byte dev 00a0
 addr 09 returns 0a
spd_rea
000906C0ul  d_byte dev 00a2
 returns 0xff
========== Check present =========
00090700ul  ==============================================
spd_read_byte dev
00090740ul   00a0
 addr 02 returns 07
========== MODBANKS ==================
00090780ul  ==========================================
spd_read_byte dev 00a
000907C0ul  0
 addr 05 returns 01
========== FIELDBANKS ====================
00090800ul  ======================================
spd_read_byte dev 00a0
 a
00090840ul  ddr 11 returns 04
========== SPDNUMROWS ========================
00090880ul  ==================================
spd_read_byte dev 00a0
 addr
000908C0ul  03 returns 03
spd_read_byte dev 00a0
 addr 04 returns 0a
=======
00090900ul  === SPDBANKDENSITY =============================================
00090940ul  =========
spd_read_byte dev 00a0
 addr 1f returns 40
==========
00090980ul  BEFORT CTZ =====================================================
000909C0ul  =====
========== TEST DIMM SIZE>8 ==============================
00090A00ul  ======================
========== PAGESIZE =====================
00090A40ul  =======================================
spd_read_byte dev 00a0
 
00090A80ul  addr 04 returns 0a
========== MAXCOLADDR =======================
00090AC0ul  ===================================
========== RDMSR CF07 ======
00090B00ul  ====================================================
==========
00090B40ul  WRMSR CF07 =====================================================
00090B80ul  =====
========== ALL DONE ======================================
00090BC0ul  ======================
========== Check present ================
00090C00ul  =======================================
spd_read_byte dev 00a2
 
00090C40ul  returns 0xff
spd_read_byte dev 00a0
 addr 12 returns 10
spd_read
00090C80ul  _byte dev 00a0
 addr 17 returns 3c
spd_read_byte dev 00a0
 addr
00090CC0ul  19 returns 4b
spd_read_byte dev 00a2
 returns 0xff
spd_read_byte
00090D00ul   dev 00a0
 addr 1e returns 28
spd_read_byte dev 00a2
 returns 0x
00090D40ul  ff
spd_read_byte dev 00a0
 addr 1b returns 0f
spd_read_byte dev
00090D80ul  00a2
 returns 0xff
spd_read_byte dev 00a0
 addr 1d returns 0f
sp
00090DC0ul  d_read_byte dev 00a2
 returns 0xff
spd_read_byte dev 00a0
 addr
00090E00ul  1c returns 0a
spd_read_byte dev 00a2
 returns 0xff
spd_read_byte
00090E40ul   dev 00a0
 addr 2a returns 46
spd_read_byte dev 00a2
 returns 0x
00090E80ul  ff
spd_read_byte dev 00a0
 addr 16 returns ff
spd_read_byte dev
00090EC0ul  00a2
 returns 0xff
spd_read_byte dev 00a0
 addr 0c returns 3a
sp
00090F00ul  d_read_byte dev 00a2
 returns 0xff
done sdram set spd registers

00090F40ul  DRAM controller init done.
RAM DLL lock
done sdram enable
stage1
00090F80ul   returns
run_file returns with 0
Done RAM init code
========== D
00090FC0ul  isable_car: done wbinvd ========================================
00091000ul  ====
Enter northbridge_init_early
writeglmsr: MSR 0x10000020, va
00091040ul  l 0x20000000:0x000fff80
writeglmsr: MSR 0x10000021, val 0x200000
00091080ul  00:0x080fffe0
sizeram: _MSR MC_CF07_DATA: 10076013:00040f40
size
000910C0ul  ram: sizem 0x100MB
sysmem_init: enable for 256MBytes
Usable RAM:
00091100ul   268304383 bytes
sysmem_init: MSR 0x10000028, val 0x2000000f:0xf
00091140ul  df00100
sizeram: _MSR MC_CF07_DATA: 10076013:00040f40
sizeram: s
00091180ul  izem 0x100MB
SMMGL0Init: 268304384 bytes
SMMGL0Init: offset is 0
000911C0ul  x80400000
SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0

00091200ul  writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003
writeglmsr
00091240ul  : MSR 0x40000020, val 0x20000000:0x000fff80
writeglmsr: MSR 0x40
00091280ul  000021, val 0x20000000:0x080fffe0
sizeram: _MSR MC_CF07_DATA: 10
000912C0ul  076013:00040f40
sizeram: sizem 0x100MB
sysmem_init: enable for 2
00091300ul  56MBytes
Usable RAM: 268304383 bytes
sysmem_init: MSR 0x4000002a
00091340ul  , val 0x2000000f:0xfdf00100
SMMGL1Init:
SMMGL1Init: MSR 0x400000
00091380ul  23, val 0x20000080:0x400fffe0
writeglmsr: MSR 0x40000080, val 0x
000913C0ul  00000000:0x00000001
writeglmsr: MSR 0x400000e3, val 0x60000000:0
00091400ul  x033000f0
CPU_RCONF_DEFAULT (1808): 0x04FFFC02:0x10FFDF00
CPU_RC
00091440ul  ONF_BYPASS (180A): 0x00000000 : 0x00000000
L2 cache enabled
GLPC
00091480ul  I R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000
GLPCI R2: syste
000914C0ul  m msr.lo 0x80400120 msr.hi 0x8041f000
Exit northbridge_init_earl
00091500ul  y
========== disable_car: done =================================
00091540ul  ==================
LAR: Attempting to open 'normal/stage2/segmen
00091580ul  t0'.
LAR: Start 0xfff80000 len 0x80000
LAR: seen member normal/p
000915C0ul  ayload/segment0
LAR: seen member normal/payload/segment1
LAR: se
00091600ul  en member normal/payload/segment2
LAR: seen member normal/option
00091640ul  _table
LAR: seen member normal/stage2/segment0
LAR: CHECK normal
00091680ul  /stage2/segment0 @ 0xfff887b0
start 0xfff88800 len 110 reallen 1
000916C0ul  91796 compression 1 entry 0x00002000 loadaddress 0x0000b8a0
LAR:
00091700ul   Compression algorithm #1 used
LAR: Attempting to open 'normal/s
00091740ul  tage2/segment1'.
LAR: Start 0xfff80000 len 0x80000
LAR: seen mem
00091780ul  ber normal/payload/segment0
LAR: seen member normal/payload/segm
000917C0ul  ent1
LAR: seen member normal/payload/segment2
LAR: seen member n
00091800ul  ormal/option_table
LAR: seen member normal/stage2/segment0
LAR:
00091840ul  seen member normal/stage2/segment1
LAR: CHECK normal/stage2/segm
00091880ul  ent1 @ 0xfff88870
start 0xfff888c0 len 17069 reallen 32284 compr
000918C0ul  ession 1 entry 0x00002000 loadaddress 0x00002000
LAR: Compressio
00091900ul  n algorithm #1 used
LAR: Attempting to open 'normal/stage2/segme
00091940ul  nt2'.
LAR: Start 0xfff80000 len 0x80000
LAR: seen member normal/
00091980ul  payload/segment0
LAR: seen member normal/payload/segment1
LAR: s
000919C0ul  een member normal/payload/segment2
LAR: seen member normal/optio
00091A00ul  n_table
LAR: seen member normal/stage2/segment0
LAR: seen member
00091A40ul   normal/stage2/segment1
LAR: seen member normal/stage2/segment2

00091A80ul  LAR: CHECK normal/stage2/segment2 @ 0xfff8cb70
start 0xfff8cbc0
00091AC0ul  len 437 reallen 6300 compression 1 entry 0x00002000 loadaddress
00091B00ul  0x0000a000
LAR: Compression algorithm #1 used
LAR: Attempting to
00091B40ul   open 'normal/stage2/segment3'.
LAR: Start 0xfff80000 len 0x8000
00091B80ul  0
LAR: seen member normal/payload/segment0
LAR: seen member norm
00091BC0ul  al/payload/segment1
LAR: seen member normal/payload/segment2
LAR
00091C00ul  : seen member normal/option_table
LAR: seen member normal/stage2
00091C40ul  /segment0
LAR: seen member normal/stage2/segment1
LAR: seen memb
00091C80ul  er normal/stage2/segment2
LAR: seen member normal/initram/segmen
00091CC0ul  t0
LAR: seen member blob/vsa
LAR: seen member bootblock
LAR: Fil
00091D00ul  e not found!
LAR: load_file: No such file 'normal/stage2/segment
00091D40ul  3'
LAR: load_file_segments: All loaded, entry 0x00002000
find_co
00091D80ul  nstructor: check all_constructors[i] 0x0000b700
find_constructor
00091DC0ul  : cons 0x0000b700, cons id PCI_DOMAIN: 1022:2080
find_constructo
00091E00ul  r: cons 0x0000b714, cons id APIC_CLUSTER: 1022:2080
find_constru
00091E40ul  ctor: cons 0x0000b728, cons id PCI: 1022:2080
find_constructor:
00091E80ul  check all_constructors[i] 0x0000b700
find_constructor: cons 0x00
00091EC0ul  00b700, cons id PCI_DOMAIN: 1022:2080
find_constructor: cons 0x0
00091F00ul  000b714, cons id APIC_CLUSTER: 1022:2080
find_constructor: cons
00091F40ul  0x0000b728, cons id PCI: 1022:2080
find_constructor: check all_c
00091F80ul  onstructors[i] 0x0000b700
find_constructor: cons 0x0000b700, con
00091FC0ul  s id PCI_DOMAIN: 1022:2080
find_constructor: cons 0x0000b714, co
00092000ul  ns id APIC_CLUSTER: 1022:2080
find_constructor: cons 0x0000b728,
00092040ul   cons id PCI: 1022:2080
find_constructor: check all_constructors
00092080ul  [i] 0x0000b820
find_constructor: cons 0x0000b820, cons id PCI: 1
000920C0ul  022:2090
find_constructor: check all_constructors[i] 0x0000b700

00092100ul  find_constructor: cons 0x0000b700, cons id PCI_DOMAIN: 1022:2080
00092140ul 
find_constructor: cons 0x0000b714, cons id APIC_CLUSTER: 1022:2
00092180ul  080
find_constructor: cons 0x0000b728, cons id PCI: 1022:2080
fi
000921C0ul  nd_constructor: check all_constructors[i] 0x0000b700
find_constr
00092200ul  uctor: cons 0x0000b700, cons id PCI_DOMAIN: 1022:2080
find_const
00092240ul  ructor: cons 0x0000b714, cons id APIC_CLUSTER: 1022:2080
find_co
00092280ul  nstructor: cons 0x0000b728, cons id PCI: 1022:2080
find_construc
000922C0ul  tor: check all_constructors[i] 0x0000b700
find_constructor: cons
00092300ul   0x0000b700, cons id PCI_DOMAIN: 1022:2080
find_constructor: con
00092340ul  s 0x0000b714, cons id APIC_CLUSTER: 1022:2080
find_constructor:
00092380ul  cons 0x0000b728, cons id PCI: 1022:2080
find_constructor: check
000923C0ul  all_constructors[i] 0x0000b820
find_constructor: cons 0x0000b820
00092400ul  , cons id PCI: 1022:2090
find_constructor: check all_constructor
00092440ul  s[i] 0x0000b700
find_constructor: cons 0x0000b700, cons id PCI_D
00092480ul  OMAIN: 1022:2080
find_constructor: cons 0x0000b714, cons id APIC
000924C0ul  _CLUSTER: 1022:2080
find_constructor: cons 0x0000b728, cons id P
00092500ul  CI: 1022:2080
find_constructor: check all_constructors[i] 0x0000
00092540ul  b700
find_constructor: cons 0x0000b700, cons id PCI_DOMAIN: 1022
00092580ul  :2080
find_constructor: cons 0x0000b714, cons id APIC_CLUSTER: 1
000925C0ul  022:2080
find_constructor: cons 0x0000b728, cons id PCI: 1022:20
00092600ul  80
find_constructor: check all_constructors[i] 0x0000b700
find_c
00092640ul  onstructor: cons 0x0000b700, cons id PCI_DOMAIN: 1022:2080
find_
00092680ul  constructor: cons 0x0000b714, cons id APIC_CLUSTER: 1022:2080
fi
000926C0ul  nd_constructor: cons 0x0000b728, cons id PCI: 1022:2080
find_con
00092700ul  structor: check all_constructors[i] 0x0000b820
find_constructor:
00092740ul   cons 0x0000b820, cons id PCI: 1022:2090
find_constructor: check
00092780ul   all_constructors[i] 0x0000b700
find_constructor: cons 0x0000b70
000927C0ul  0, cons id PCI_DOMAIN: 1022:2080
find_constructor: cons 0x0000b7
00092800ul  14, cons id APIC_CLUSTER: 1022:2080
find_constructor: cons 0x000
00092840ul  0b728, cons id PCI: 1022:2080
find_constructor: match
find_const
00092880ul  ructor: check all_constructors[i] 0x0000b700
find_constructor: c
000928C0ul  ons 0x0000b700, cons id PCI_DOMAIN: 1022:2080
find_constructor:
00092900ul  cons 0x0000b714, cons id APIC_CLUSTER: 1022:2080
find_constructo
00092940ul  r: cons 0x0000b728, cons id PCI: 1022:2080
find_constructor: che
00092980ul  ck all_constructors[i] 0x0000b700
find_constructor: cons 0x0000b
000929C0ul  700, cons id PCI_DOMAIN: 1022:2080
find_constructor: cons 0x0000
00092A00ul  b714, cons id APIC_CLUSTER: 1022:2080
find_constructor: cons 0x0
00092A40ul  000b728, cons id PCI: 1022:2080
find_constructor: check all_cons
00092A80ul  tructors[i] 0x0000b700
find_constructor: cons 0x0000b700, cons i
00092AC0ul  d PCI_DOMAIN: 1022:2080
find_constructor: cons 0x0000b714, cons
00092B00ul  id APIC_CLUSTER: 1022:2080
find_constructor: cons 0x0000b728, co
00092B40ul  ns id PCI: 1022:2080
find_constructor: check all_constructors[i]
00092B80ul   0x0000b820
find_constructor: cons 0x0000b820, cons id PCI: 1022
00092BC0ul  :2090
find_constructor: match
find_constructor: check all_constr
00092C00ul  uctors[i] 0x0000b700
find_constructor: cons 0x0000b700, cons id
00092C40ul  PCI_DOMAIN: 1022:2080
find_constructor: cons 0x0000b714, cons id
00092C80ul   APIC_CLUSTER: 1022:2080
find_constructor: cons 0x0000b728, cons
00092CC0ul   id PCI: 1022:2080
find_constructor: check all_constructors[i] 0
00092D00ul  x0000b700
find_constructor: cons 0x0000b700, cons id PCI_DOMAIN:
00092D40ul   1022:2080
find_constructor: cons 0x0000b714, cons id APIC_CLUST
00092D80ul  ER: 1022:2080
find_constructor: cons 0x0000b728, cons id PCI: 10
00092DC0ul  22:2080
find_constructor: check all_constructors[i] 0x0000b700
f
00092E00ul  ind_constructor: cons 0x0000b700, cons id PCI_DOMAIN: 1022:2080

00092E40ul  find_constructor: cons 0x0000b714, cons id APIC_CLUSTER: 1022:20
00092E80ul  80
find_constructor: cons 0x0000b728, cons id PCI: 1022:2080
fin
00092EC0ul  d_constructor: check all_constructors[i] 0x0000b820
find_constru
00092F00ul  ctor: cons 0x0000b820, cons id PCI: 1022:2090
find_constructor:
00092F40ul  check all_constructors[i] 0x0000b700
find_constructor: cons 0x00
00092F80ul  00b700, cons id PCI_DOMAIN: 1022:2080
find_constructor: match
Ph
00092FC0ul  ase 1: Very early setup...
Phase 1: done
Show all devs...
root(R
00093000ul  oot Device): enabled 1 have_resources 0 initialized 0
cpus: Unkn
00093040ul  own device path type: 0
cpus(): enabled 1 have_resources 0 initi
00093080ul  alized 0
apic: Unknown device path type: 0
apic(): enabled 1 hav
000930C0ul  e_resources 0 initialized 0
device0_0(PCI: 00:01.0): enabled 1 h
00093100ul  ave_resources 0 initialized 0
southbridge(PCI: 00:0f.0): enabled
00093140ul   1 have_resources 0 initialized 0
superio: Unknown device path t
00093180ul  ype: 0
superio(): enabled 0 have_resources 0 initialized 0
domai
000931C0ul  n0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0
P
00093200ul  hase 2: Early setup...
dev_phase2: dev root: ops 0x00008ee0 ops-
00093240ul  >phase2_setup_scan_bus 0x00000000
dev_phase2: dev cpus: ops 0x00
00093280ul  000000 ops->phase2_setup_scan_bus 0x00000000
dev_phase2: dev api
000932C0ul  c: ops 0x00000000 ops->phase2_setup_scan_bus 0x00000000
dev_phas
00093300ul  e2: dev device0_0: ops 0x0000b7e0 ops->phase2_setup_scan_bus 0x0
00093340ul  0000000
dev_phase2: dev southbridge: ops 0x0000b860 ops->phase2_
00093380ul  setup_scan_bus 0x00000000
dev_phase2: dev superio: ops 0x0000000
000933C0ul  0 ops->phase2_setup_scan_bus 0x00000000
dev_phase2: dev domain0:
00093400ul   ops 0x0000b760 ops->phase2_setup_scan_bus 0x00006da5
Calling ph
00093440ul  ase2 phase2_setup_scan_bus...
 >> Entering northbridge.c: geodelx
00093480ul  _pci_domain_phase2
dev_find_device: find PCI: 1022:2090
dev_id_s
000934C0ul  tring: Unknown device ID type: 0
Check Unknown
dev_id_string: Un
00093500ul  known device ID type: 0
Check Unknown
Check APIC: 1022:2080
Chec
00093540ul  k PCI: 1022:2080
Check PCI: 1022:2090
found
Not Doing chipset_fl
00093580ul  ash_setup()
Before VSA:
do_vsmbios
LAR: Attempting to open 'blob
000935C0ul  /vsa'.
LAR: Start 0xfff80000 len 0x80000
LAR: seen member normal
00093600ul  /payload/segment0
LAR: seen member normal/payload/segment1
LAR:
00093640ul  seen member normal/payload/segment2
LAR: seen member normal/opti
00093680ul  on_table
LAR: seen member normal/stage2/segment0
LAR: seen membe
000936C0ul  r normal/stage2/segment1
LAR: seen member normal/stage2/segment2
00093700ul 
LAR: seen member normal/initram/segment0
LAR: seen member blob/
00093740ul  vsa
LAR: CHECK blob/vsa @ 0xfff8e2d0
start 0xfff8e310 len 57504
00093780ul  reallen 57504 compression 0 entry 0x00000000 loadaddress 0x00000
000937C0ul  000
LAR: Compression algorithm #0 used
buf ilen 57504 real len 5
00093800ul  7504ld
buf 0x00060000 *buf 186 buf[256k] 244
buf[0x20] signature
00093840ul   is b0:10:e6:80
Call real_mode_switch_call_vsm

.... I stopped at VSA init. Good enough for me.



-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors







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