[coreboot] r611 - in coreboot-v3: device include include/arch/x86 include/device northbridge/intel/i440bxemulation

svn at coreboot.org svn at coreboot.org
Tue Feb 19 01:34:33 CET 2008 

Author: hailfinger
Date: 2008-02-19 01:34:32 +0100 (Tue, 19 Feb 2008)
New Revision: 611

Modified:
   coreboot-v3/device/smbus_ops.c
   coreboot-v3/include/arch/x86/msr.h
   coreboot-v3/include/arch/x86/pci_ops.h
   coreboot-v3/include/arch/x86/pirq_routing.h
   coreboot-v3/include/device/agp.h
   coreboot-v3/include/device/cardbus.h
   coreboot-v3/include/device/hypertransport.h
   coreboot-v3/include/device/pci_rom.h
   coreboot-v3/include/device/pcie.h
   coreboot-v3/include/device/pcix.h
   coreboot-v3/include/device/smbus.h
   coreboot-v3/include/post_code.h
   coreboot-v3/include/spd.h
   coreboot-v3/northbridge/intel/i440bxemulation/i440bx.h
Log:
A lot of the v3 header files require other header files to be #included 
before they can be #included. That is completely counter-intuitive. Add 
necessary #includes to the header files themselves.

Fix a few cases where nonexisting files were #included.

Compile tested on Qemu and Alix1C.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: coreboot-v3/device/smbus_ops.c
===================================================================
--- coreboot-v3/device/smbus_ops.c	2008-02-18 20:44:54 UTC (rev 610)
+++ coreboot-v3/device/smbus_ops.c	2008-02-19 00:34:32 UTC (rev 611)
@@ -20,7 +20,6 @@
  */
 
 #include <console.h>
-#include <stdint.h>
 #include <device/device.h>
 #include <device/path.h>
 #include <device/smbus.h>

Modified: coreboot-v3/include/arch/x86/msr.h
===================================================================
--- coreboot-v3/include/arch/x86/msr.h	2008-02-18 20:44:54 UTC (rev 610)
+++ coreboot-v3/include/arch/x86/msr.h	2008-02-19 00:34:32 UTC (rev 611)
@@ -20,6 +20,8 @@
 #ifndef CPU_X86_MSR_H
 #define CPU_X86_MSR_H
 
+#include <types.h>
+
 /* standard MSR operations, everyone has written these one hundred times */
 struct msr {
 	u32 lo;

Modified: coreboot-v3/include/arch/x86/pci_ops.h
===================================================================
--- coreboot-v3/include/arch/x86/pci_ops.h	2008-02-18 20:44:54 UTC (rev 610)
+++ coreboot-v3/include/arch/x86/pci_ops.h	2008-02-19 00:34:32 UTC (rev 611)
@@ -17,6 +17,8 @@
 #ifndef ARCH_X86_PCI_OPS_H
 #define ARCH_X86_PCI_OPS_H
 
+#include <device/device.h>
+
 extern const struct pci_bus_operations pci_cf8_conf1;
 extern const struct pci_bus_operations pci_cf8_conf2;
 

Modified: coreboot-v3/include/arch/x86/pirq_routing.h
===================================================================
--- coreboot-v3/include/arch/x86/pirq_routing.h	2008-02-18 20:44:54 UTC (rev 610)
+++ coreboot-v3/include/arch/x86/pirq_routing.h	2008-02-19 00:34:32 UTC (rev 611)
@@ -21,6 +21,8 @@
 #ifndef ARCH_PIRQ_ROUTING_H
 #define ARCH_PIRQ_ROUTING_H
 
+#include <types.h>
+
 #define PIRQ_SIGNATURE	(('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
 #define PIRQ_VERSION 0x0100
 

Modified: coreboot-v3/include/device/agp.h
===================================================================
--- coreboot-v3/include/device/agp.h	2008-02-18 20:44:54 UTC (rev 610)
+++ coreboot-v3/include/device/agp.h	2008-02-19 00:34:32 UTC (rev 611)
@@ -19,6 +19,8 @@
 #ifndef DEVICE_AGP_H
 #define DEVICE_AGP_H
 
+#include <device/device.h>
+
 unsigned int agp_scan_bus(struct bus *bus, 
 	unsigned min_devfn, unsigned max_devfn, unsigned int max);
 unsigned int agp_scan_bridge(struct device *dev, unsigned int max);

Modified: coreboot-v3/include/device/cardbus.h
===================================================================
--- coreboot-v3/include/device/cardbus.h	2008-02-18 20:44:54 UTC (rev 610)
+++ coreboot-v3/include/device/cardbus.h	2008-02-19 00:34:32 UTC (rev 611)
@@ -19,6 +19,8 @@
 #ifndef DEVICE_CARDBUS_H
 #define DEVICE_CARDBUS_H
 
+#include <device/device.h>
+
 void cardbus_read_resources(struct device *dev);
 unsigned int cardbus_scan_bus(struct bus *bus, 
 	unsigned min_devfn, unsigned max_devfn, unsigned int max);

Modified: coreboot-v3/include/device/hypertransport.h
===================================================================
--- coreboot-v3/include/device/hypertransport.h	2008-02-18 20:44:54 UTC (rev 610)
+++ coreboot-v3/include/device/hypertransport.h	2008-02-19 00:34:32 UTC (rev 611)
@@ -18,6 +18,7 @@
 #ifndef DEVICE_HYPERTRANSPORT_H
 #define DEVICE_HYPERTRANSPORT_H
 
+#include <device/device.h>
 #include <device/hypertransport_def.h>
 
 unsigned int hypertransport_scan_chain(struct bus *bus, 

Modified: coreboot-v3/include/device/pci_rom.h
===================================================================
--- coreboot-v3/include/device/pci_rom.h	2008-02-18 20:44:54 UTC (rev 610)
+++ coreboot-v3/include/device/pci_rom.h	2008-02-19 00:34:32 UTC (rev 611)
@@ -19,6 +19,7 @@
 
 #include <types.h>
 #include <byteorder.h>
+#include <device/device.h>
 
 #define PCI_ROM_HDR 0xAA55
 #define PCI_DATA_HDR (u32) ( ('R' << 24) | ('I' << 16) | ('C' << 8) | 'P' )

Modified: coreboot-v3/include/device/pcie.h
===================================================================
--- coreboot-v3/include/device/pcie.h	2008-02-18 20:44:54 UTC (rev 610)
+++ coreboot-v3/include/device/pcie.h	2008-02-19 00:34:32 UTC (rev 611)
@@ -20,6 +20,8 @@
 #ifndef DEVICE_PCIE_H
 #define DEVICE_PCIE_H
 
+#include <device/device.h>
+
 unsigned int pcie_scan_bus(struct bus *bus, 
 	unsigned min_devfn, unsigned max_devfn, unsigned int max);
 unsigned int pcie_scan_bridge(struct device *dev, unsigned int max);

Modified: coreboot-v3/include/device/pcix.h
===================================================================
--- coreboot-v3/include/device/pcix.h	2008-02-18 20:44:54 UTC (rev 610)
+++ coreboot-v3/include/device/pcix.h	2008-02-19 00:34:32 UTC (rev 611)
@@ -18,6 +18,8 @@
 #ifndef DEVICE_PCIX_H
 #define DEVICE_PCIX_H
 
+#include <device/device.h>
+
 /* (c) 2005 Linux Networx GPL see COPYING for details */
 
 unsigned int pcix_scan_bus(struct bus *bus, 

Modified: coreboot-v3/include/device/smbus.h
===================================================================
--- coreboot-v3/include/device/smbus.h	2008-02-18 20:44:54 UTC (rev 610)
+++ coreboot-v3/include/device/smbus.h	2008-02-19 00:34:32 UTC (rev 611)
@@ -18,7 +18,6 @@
 #ifndef DEVICE_SMBUS_H
 #define DEVICE_SMBUS_H
 
-#include <stdint.h>
 #include <device/device.h>
 #include <device/path.h>
 #include <device/smbus_def.h>

Modified: coreboot-v3/include/post_code.h
===================================================================
--- coreboot-v3/include/post_code.h	2008-02-18 20:44:54 UTC (rev 610)
+++ coreboot-v3/include/post_code.h	2008-02-19 00:34:32 UTC (rev 611)
@@ -21,6 +21,7 @@
 #ifndef POST_CODE_H
 #define POST_CODE_H
 
+#include <types.h>
 #include <shared.h>
 
 SHARED(post_code, void, u8 value);

Modified: coreboot-v3/include/spd.h
===================================================================
--- coreboot-v3/include/spd.h	2008-02-18 20:44:54 UTC (rev 610)
+++ coreboot-v3/include/spd.h	2008-02-19 00:34:32 UTC (rev 611)
@@ -36,6 +36,8 @@
 #ifndef _SPD_H_
 #define _SPD_H_
 
+#include <types.h>
+
 /* Byte numbers. */
 #define SPD_NUM_MANUFACTURER_BYTES          0  /* Number of bytes used by module manufacturer */
 #define SPD_TOTAL_SPD_MEMORY_SIZE           1  /* Total SPD memory size */

Modified: coreboot-v3/northbridge/intel/i440bxemulation/i440bx.h
===================================================================
--- coreboot-v3/northbridge/intel/i440bxemulation/i440bx.h	2008-02-18 20:44:54 UTC (rev 610)
+++ coreboot-v3/northbridge/intel/i440bxemulation/i440bx.h	2008-02-19 00:34:32 UTC (rev 611)
@@ -21,6 +21,8 @@
 #ifndef NORTHBRIDGE_INTEL_I440BXEMULATION_I440BX_H
 #define NORTHBRIDGE_INTEL_I440BXEMULATION_I440BX_H
 
+#include <device/device.h>
+
 /*
  * Datasheet:
  *   - Name: Intel 440BX AGPset: 82443BX Host Bridge/Controller

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