[coreboot] Fixing the flashrom problem on m57sli v2.0 (issue #87?)

[Florentin Demetrescu]

Hello,

I propose this patch :

Index: LinuxBIOSv2_spi_debug/src/southbridge/nvidia/mcp55/mcp55_lpc.c
===================================================================
--- LinuxBIOSv2_spi_debug/src/southbridge/nvidia/mcp55/mcp55_lpc.c	(revision
3050)
+++ LinuxBIOSv2_spi_debug/src/southbridge/nvidia/mcp55/mcp55_lpc.c	(working
copy)
@@ -161,11 +161,15 @@

 static void lpc_init(device_t dev)
 {
+	struct southbridge_nvidia_mcp55_config *conf;
+	uint32_t dword;
 	uint8_t byte;
 	uint8_t byte_old;
 	int on;
 	int nmi_option;

+	conf = dev->chip_info;
+
 	lpc_common_init(dev);

 #if 0
@@ -238,6 +242,18 @@
 	/* Initialize the High Precision Event Timers */
 //	enable_hpet(dev);

+	/* Enables the decoding of the IO addresses to the flash SPI interface
+	 (if present into the SIO) */
+	if (conf->spi_sio_enable) {
+		dword = pci_read_config32(dev, 0xa0);
+		dword |= (1<<30);
+		pci_write_config32(dev, 0xa0, dword);
+
+		/* FIXME : really dirty! It seems that the IO addr range for the SPI IF.
+		 HAS to be set into the 0xb0 or 0xb4 reg which conflicts strongly with
+		 mcp55_lpc_enable_childrens_resources() */
+		pci_write_config32(dev, conf->spi_sio_pcireg, conf->spi_sio_iorange);
+	}
 }

 static void mcp55_lpc_read_resources(device_t dev)
Index: LinuxBIOSv2_spi_debug/src/southbridge/nvidia/mcp55/chip.h
===================================================================
--- LinuxBIOSv2_spi_debug/src/southbridge/nvidia/mcp55/chip.h	(revision 3050)
+++ LinuxBIOSv2_spi_debug/src/southbridge/nvidia/mcp55/chip.h	(working copy)
@@ -28,8 +28,11 @@
 	unsigned int ide1_enable : 1;
 	unsigned int sata0_enable : 1;
 	unsigned int sata1_enable : 1;
+	unsigned int spi_sio_enable : 1;
 	unsigned int mac_eeprom_smbus;
 	unsigned int mac_eeprom_addr;
+	unsigned int spi_sio_pcireg;
+	unsigned int spi_sio_iorange;
 };
 struct chip_operations;
 extern struct chip_operations southbridge_nvidia_mcp55_ops;
Index: LinuxBIOSv2_spi_debug/src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- LinuxBIOSv2_spi_debug/src/mainboard/gigabyte/m57sli/Config.lb	(revision
3050)
+++ LinuxBIOSv2_spi_debug/src/mainboard/gigabyte/m57sli/Config.lb	(working copy)
@@ -403,6 +403,9 @@
                         	        register "sata1_enable" = "1"
 					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 					register "mac_eeprom_addr" = "0x51"
+					register "spi_sio_enable" = "1"
+					register "spi_sio_pcireg" = "0xb0"
+					register "spi_sio_iorange" = "0x085f0800"
 				end
 			end #  device pci 18.0
 			device pci 18.0 on end # Link 1

Btw is this related to the issue #87 in Issuetracker? (should a new ticket be
created especially for this issue?)

Thanks a lot for the help in resolving this issue to all the coreboot team!
 Florentin