[coreboot] [LinuxBIOS] Intel 3100 chipset, version 2
Uwe Hermann
uwe at hermann-uwe.de
Tue Jan 22 19:29:16 CET 2008
Hi,
On Tue, Jan 22, 2008 at 05:53:46PM +0100, Carl-Daniel Hailfinger wrote:
> > There's no urgency, but I'm wondering if there's anything I can do to help.
>
> I'm sorry, but I'm swamped with thesis work right now and will not have
> time to review until end of February at the earliest?
>
> Can you find someone else for the review?
See below:
> Index: LinuxBIOSv2-3023/src/superio/intel/i3100/Config.lb
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/superio/intel/i3100/Config.lb
Does the Super I/O have a special name? AFAICS it's not integrated into
the 3100 chipset, but rather an external entity connected via LPC (?)
Is the vendor really Intel and the name 3100, or does it have some other
name we could use?
Either way, please split out the superio part into an extra patch, we
can review/commit that independently of the rest of the code.
> @@ -0,0 +1,25 @@
> +##
> +## This file is part of the LinuxBIOS project.
Please rebase the patch against the latest coreboot svn, and also rename
LinuxBIOS occurences to coreboot where needed. We could also do that
in an extra step after the commit, though, if you prefer that.
> +##
> +## Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
Drop my line, this file is utterly trivial. No need to carry over
copyright lines for such trivial stuff.
> +##
> +## Copyright (C) 2007 Arastra, Inc.
Copyright is owned by Arastra (your employer, I assume?) or by you
personally? If the latter, please fix the lines. If not, this is ok.
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> +##
> +
> +config chip.h
> +object superio.o
> +
> Index: LinuxBIOSv2-3023/src/superio/intel/i3100/chip.h
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/superio/intel/i3100/chip.h
> @@ -0,0 +1,35 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
Drop this, see above.
> + *
> + * Copyright (C) 2007 Arastra, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> + */
> +
> +#ifndef _SUPERIO_INTEL_I3100
SUPERIO_INTEL_I3100_CHIP_H for consistency.
> +#define _SUPERIO_INTEL_I3100
Ditto.
> +
> +#include <device/device.h>
> +#include <uart8250.h>
> +
> +extern struct chip_operations superio_intel_i3100_ops;
> +
> +struct superio_intel_i3100_config {
> + struct uart8250 com1, com2;
> +};
> +
> +#endif /* _SUPERIO_INTEL_I3100 */
Ditto.
> Index: LinuxBIOSv2-3023/src/superio/intel/i3100/i3100.h
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/superio/intel/i3100/i3100.h
> @@ -0,0 +1,27 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
Drop, see above.
> + *
> + * Copyright (C) 2007 Arastra, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> + */
> +
> +/* Datasheet: http://www.intel.com/design/intarch/datashts/313458.htm */
> +
> +#define I3100_SP1 0x04 /* Com1 */
> +#define I3100_SP2 0x05 /* Com2 */
> +#define I3100_WDT 0x06 /* Watchdog timer */
> Index: LinuxBIOSv2-3023/src/superio/intel/i3100/i3100_early_serial.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/superio/intel/i3100/i3100_early_serial.c
> @@ -0,0 +1,54 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
Drop.
> + *
> + * Copyright (C) 2007 Arastra, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> + */
> +
> +#include <arch/romcc_io.h>
> +#include "i3100.h"
> +
> +static void i3100_sio_write(uint8_t port, uint8_t ldn, uint8_t index,
> + uint8_t value)
Feel free to switch to the shorter u8, u16 etc. everywhere in the code.
No hurry though, we can do that later in an extra commit.
> +{
> + outb(0x07, port);
> + outb(ldn, port + 1);
> + outb(index, port);
> + outb(value, port + 1);
> +}
> +
> +static void i3100_enable_serial(uint8_t port, uint8_t ldn, uint16_t iobase)
> +{
> + /* Enter configuration state */
> + outb(0x80, port);
> + outb(0x86, port);
> +
> + /* Enable serial port */
> + i3100_sio_write(port, ldn, 0x30, 0x01);
> +
> + /* Set serial port IO region */
> + i3100_sio_write(port, ldn, 0x60, (iobase >> 8) & 0xff);
> + i3100_sio_write(port, ldn, 0x61, iobase & 0xff);
> +
> + /* Enable device interrupts, set UART_CLK predivide to 26 */
> + i3100_sio_write(port, 0x00, 0x29, 0x0b);
> +
> + /* Exit configuration state */
> + outb(0x68, port);
> + outb(0x08, port);
> +}
> Index: LinuxBIOSv2-3023/src/superio/intel/i3100/superio.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/superio/intel/i3100/superio.c
> @@ -0,0 +1,113 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
> + *
> + * Copyright (C) 2007 AMD
> + * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
> + *
> + * Copyright (C) 2007 Arastra, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> + */
> +
> +#include <device/device.h>
> +#include <device/pnp.h>
> +#include <uart8250.h>
> +#include "chip.h"
> +#include "i3100.h"
> +#include <arch/io.h>
> +
> +static void pnp_enter_ext_func_mode(device_t dev)
> +{
> + outb(0x80, dev->path.u.pnp.port);
> + outb(0x86, dev->path.u.pnp.port);
> +}
> +
> +static void pnp_exit_ext_func_mode(device_t dev)
> +{
> + outb(0x68, dev->path.u.pnp.port);
> + outb(0x08, dev->path.u.pnp.port);
> +}
> +
> +static void i3100_init(device_t dev)
> +{
> + struct superio_intel_i3100_config *conf;
> + struct resource *res0;
> +
> + if (!dev->enabled) {
> + return;
> + }
> +
> + conf = dev->chip_info;
> +
> + switch (dev->path.u.pnp.device) {
> + case I3100_SP1:
> + res0 = find_resource(dev, PNP_IDX_IO0);
> + init_uart8250(res0->base, &conf->com1);
> + break;
> + case I3100_SP2:
> + res0 = find_resource(dev, PNP_IDX_IO0);
> + init_uart8250(res0->base, &conf->com2);
> + break;
> + }
> +}
> +
> +static void i3100_pnp_set_resources(device_t dev)
> +{
> + pnp_enter_ext_func_mode(dev);
> + pnp_set_resources(dev);
> + pnp_exit_ext_func_mode(dev);
> +}
> +
> +static void i3100_pnp_enable_resources(device_t dev)
> +{
> + pnp_enter_ext_func_mode(dev);
> + pnp_enable_resources(dev);
> + pnp_exit_ext_func_mode(dev);
> +}
> +
> +static void i3100_pnp_enable(device_t dev)
> +{
> + pnp_enter_ext_func_mode(dev);
> + pnp_set_logical_device(dev);
> + pnp_set_enable(dev, dev->enabled);
> + pnp_exit_ext_func_mode(dev);
> +}
> +
> +static struct device_operations ops = {
> + .read_resources = pnp_read_resources,
> + .set_resources = i3100_pnp_set_resources,
> + .enable_resources = i3100_pnp_enable_resources,
> + .enable = i3100_pnp_enable,
> + .init = i3100_init,
> +};
> +
> +static struct pnp_info pnp_dev_info[] = {
> + { &ops, I3100_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
> + { &ops, I3100_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
> +};
> +
> +static void enable_dev(struct device *dev)
> +{
> + pnp_enable_devices(dev, &ops,
> + sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
You can use ARRAY_SIZE here (it's in stdlib.h)
> +}
> +
> +struct chip_operations superio_intel_i3100_ops = {
> + CHIP_NAME("Intel 3100 Super I/O")
> + .enable_dev = enable_dev,
> +};
> +
> Index: LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/Config.lb
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/Config.lb
Add the usual license header, please.
> @@ -0,0 +1,178 @@
> +##
> +## Only use the option table in a normal image
> +##
> +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
> +
> +##
> +## Compute the location and size of where this firmware image
> +## (linuxBIOS plus bootloader) will live in the boot rom chip.
> +##
> +if USE_FALLBACK_IMAGE
> + default ROM_SECTION_SIZE = FALLBACK_SIZE
> + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
> +else
> + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
> + default ROM_SECTION_OFFSET = 0
> +end
> +
> +##
> +## Compute the start location and size size of
> +## The linuxBIOS bootloader.
> +##
> +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
> +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
> +
> +##
> +## Compute where this copy of linuxBIOS will start in the boot rom
> +##
> +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
> +
> +##
> +## Compute a range of ROM that can cached to speed up linuxBIOS,
> +## execution speed.
> +##
> +## XIP_ROM_SIZE must be a power of 2.
> +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
> +##
> +default XIP_ROM_SIZE=131072
> +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
> +
> +##
> +## Set all of the defaults for an x86 architecture
> +##
> +
> +arch i386 end
> +
> +##
> +## Build the objects we have code for in this directory.
> +##
> +
> +driver mainboard.o
> +if HAVE_MP_TABLE object mptable.o end
> +if HAVE_PIRQ_TABLE object irq_tables.o end
> +object reset.o
> +
> +##
> +## Romcc output
> +##
> +makerule ./failover.E
> + depends "$(MAINBOARD)/failover.c ./romcc"
> + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
> +end
> +
> +makerule ./failover.inc
> + depends "$(MAINBOARD)/failover.c ./romcc"
> + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
> +end
> +
> +makerule ./auto.E
> + depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
> + action "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
> +end
> +makerule ./auto.inc
> + depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
> + action "./romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
> +end
> +
> +##
> +## Build our 16 bit and 32 bit linuxBIOS entry code
> +##
> +mainboardinit cpu/x86/16bit/entry16.inc
> +mainboardinit cpu/x86/32bit/entry32.inc
> +ldscript /cpu/x86/16bit/entry16.lds
> +ldscript /cpu/x86/32bit/entry32.lds
> +
> +##
> +## Build our reset vector (This is where linuxBIOS is entered)
> +##
> +if USE_FALLBACK_IMAGE
> + mainboardinit cpu/x86/16bit/reset16.inc
> + ldscript /cpu/x86/16bit/reset16.lds
> +else
> + mainboardinit cpu/x86/32bit/reset32.inc
> + ldscript /cpu/x86/32bit/reset32.lds
> +end
> +
> +### Should this be in the northbridge code?
> +mainboardinit arch/i386/lib/cpu_reset.inc
> +
> +##
> +## Include an id string (For safe flashing)
> +##
> +mainboardinit arch/i386/lib/id.inc
> +ldscript /arch/i386/lib/id.lds
> +
> +###
> +### This is the early phase of linuxBIOS startup
> +### Things are delicate and we test to see if we should
> +### failover to another image.
> +###
> +if USE_FALLBACK_IMAGE
> + ldscript /arch/i386/lib/failover.lds
> + mainboardinit ./failover.inc
> +end
> +
> +###
> +### O.k. We aren't just an intermediary anymore!
> +###
> +
> +##
> +## Setup RAM
> +##
> +mainboardinit cpu/x86/fpu/enable_fpu.inc
> +mainboardinit cpu/x86/mmx/enable_mmx.inc
> +mainboardinit cpu/x86/sse/enable_sse.inc
> +mainboardinit ./auto.inc
> +mainboardinit cpu/x86/sse/disable_sse.inc
> +mainboardinit cpu/x86/mmx/disable_mmx.inc
> +
> +##
> +## Include the secondary Configuration files
> +##
> +dir /pc80
> +config chip.h
> +
> +chip northbridge/intel/i3100
> + device pci_domain 0 on
> + device pci 00.0 on end
> + device pci 00.1 on end
> + device pci 01.0 on end
> + device pci 02.0 on end
> + device pci 03.0 on end
Add comments after each line saying what is what -- makes it
easier to read and understand later.
> + chip southbridge/intel/i3100
> + register "pirq_a_d" = "0x0b070a05"
> + register "pirq_e_h" = "0x0a808080"
Please document this a bit more (add a comment).
> +
> + device pci 1c.0 on end
> + device pci 1c.1 on end
> + device pci 1c.2 on end
> + device pci 1c.3 on end
> + device pci 1d.0 on end
> + device pci 1d.1 on end
> + device pci 1d.7 on end
> + device pci 1e.0 on end
> + device pci 1e.2 on end
> + device pci 1e.3 on end
> + device pci 1f.0 on
> + chip superio/intel/i3100
> + device pnp 4e.4 on
> + io 0x60 = 0x3f8
> + irq 0x70 = 4
> + end
> + device pnp 4e.5 on
> + io 0x60 = 0x2f8
> + irq 0x70 = 3
> + end
> + end
> + end
> + device pci 1f.2 on end
> + device pci 1f.3 on end
> + device pci 1f.4 on end
> + end
> + end
> + device apic_cluster 0 on
> + chip cpu/intel/socket_mPGA479M
> + device apic 0 on end
> + end
> + end
> +end
Please post some more info on the board to the list for archival
purposes, e.g. lspci -tnvn, lspci -xxxx, etc.
I'll provide a superiotool patch later, please also send a dump
of the Super I/O then.
> Index: LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/Options.lb
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/Options.lb
Add the usual license header, please.
> @@ -0,0 +1,242 @@
> +uses HAVE_MP_TABLE
> +uses HAVE_PIRQ_TABLE
> +uses USE_FALLBACK_IMAGE
> +uses HAVE_FALLBACK_BOOT
> +uses HAVE_HARD_RESET
> +uses IRQ_SLOT_COUNT
> +uses HAVE_OPTION_TABLE
> +uses CONFIG_LOGICAL_CPUS
> +uses CONFIG_MAX_CPUS
> +uses CONFIG_IOAPIC
> +uses CONFIG_SMP
> +uses FALLBACK_SIZE
> +uses ROM_SIZE
> +uses ROM_SECTION_SIZE
> +uses ROM_IMAGE_SIZE
> +uses ROM_SECTION_SIZE
> +uses ROM_SECTION_OFFSET
> +uses CONFIG_ROM_PAYLOAD
> +uses CONFIG_ROM_PAYLOAD_START
> +uses CONFIG_COMPRESSED_PAYLOAD_LZMA
> +uses PAYLOAD_SIZE
> +uses _ROMBASE
> +uses XIP_ROM_SIZE
> +uses XIP_ROM_BASE
> +uses STACK_SIZE
> +uses HEAP_SIZE
> +uses USE_OPTION_TABLE
> +uses LB_CKS_RANGE_START
> +uses LB_CKS_RANGE_END
> +uses LB_CKS_LOC
> +uses MAINBOARD
> +uses MAINBOARD_PART_NUMBER
> +uses MAINBOARD_VENDOR
> +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
> +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
> +uses LINUXBIOS_EXTRA_VERSION
> +uses CONFIG_UDELAY_TSC
> +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
> +uses _RAMBASE
> +uses CONFIG_GDB_STUB
> +uses CONFIG_CONSOLE_SERIAL8250
> +uses TTYS0_BAUD
> +uses TTYS0_BASE
> +uses TTYS0_LCS
> +uses DEFAULT_CONSOLE_LOGLEVEL
> +uses MAXIMUM_CONSOLE_LOGLEVEL
> +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
> +uses CONFIG_CONSOLE_BTEXT
> +uses CC
> +uses HOSTCC
> +uses CROSS_COMPILE
> +uses OBJCOPY
> +uses MAX_REBOOT_CNT
> +uses USE_WATCHDOG_ON_BOOT
> +
> +
> +###
> +### Build options
> +###
> +
> +##
> +## Because we do the stutter start we need more attempts
> +##
Huh? Please expand the comment.
> +default MAX_REBOOT_CNT=8
> +
> +##
> +## Use the watchdog to break out of a lockup condition
> +##
Ditto.
> +default USE_WATCHDOG_ON_BOOT=0
> +
> +##
> +## ROM_SIZE is the size of boot ROM that this board will use.
> +##
> +default ROM_SIZE=2097152
default ROM_SIZE = 2048 * 1024
> +
> +
> +##
> +## Build code for the fallback boot
> +##
> +default HAVE_FALLBACK_BOOT=1
> +
> +##
> +## Delay timer options
> +## Use timer2
> +##
> +default CONFIG_UDELAY_TSC=1
> +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
> +
> +##
> +## Build code to reset the motherboard from linuxBIOS
> +##
> +default HAVE_HARD_RESET=1
> +
> +##
> +## Build code to export a programmable irq routing table
> +##
> +default HAVE_PIRQ_TABLE=1
> +default IRQ_SLOT_COUNT=1
> +
> +##
> +## Build code to export an x86 MP table
> +## Useful for specifying IRQ routing values
> +##
> +default HAVE_MP_TABLE=1
> +
> +##
> +## Build code to export a CMOS option table
> +##
> +default HAVE_OPTION_TABLE=1
> +
> +##
> +## Move the default LinuxBIOS cmos range off of AMD RTC registers
> +##
> +default LB_CKS_RANGE_START=49
> +default LB_CKS_RANGE_END=122
> +default LB_CKS_LOC=123
> +
> +##
> +## Build code for SMP support
> +## Only worry about 2 micro processors
> +##
> +default CONFIG_SMP=1
> +default CONFIG_MAX_CPUS=4
> +default CONFIG_LOGICAL_CPUS=0
> +
> +##
> +## Build code to setup a generic IOAPIC
> +##
> +default CONFIG_IOAPIC=1
> +
> +##
> +## Clean up the motherboard id strings
> +##
> +default MAINBOARD_PART_NUMBER="MtArvon"
default MAINBOARD_PART_NUMBER="Mt. Arvon"
> +default MAINBOARD_VENDOR= "Intel"
> +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
> +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680
Which device ID did you use here?
> +
> +###
> +### LinuxBIOS layout values
> +###
> +
> +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
> +default ROM_IMAGE_SIZE = 65536
> +
> +##
> +## Use a small 8K stack
> +##
> +default STACK_SIZE=0x2000
> +
> +##
> +## Use a small 32K heap
> +##
> +default HEAP_SIZE=0x8000
> +
> +
> +###
> +### Compute the location and size of where this firmware image
> +### (linuxBIOS plus bootloader) will live in the boot rom chip.
> +###
> +default FALLBACK_SIZE=131072
> +
> +##
> +## LinuxBIOS C code runs at this location in RAM
> +##
> +default _RAMBASE=0x00004000
> +
> +##
> +## Load the payload from the ROM
> +##
> +default CONFIG_ROM_PAYLOAD=1
> +
> +
> +###
> +### Defaults of options that you may want to override in the target config file
> +###
> +
> +##
> +## The default compiler
> +##
> +default CC="$(CROSS_COMPILE)gcc -m32"
> +default HOSTCC="gcc"
> +
> +##
> +## Disable the gdb stub by default
> +##
> +default CONFIG_GDB_STUB=0
> +
> +##
> +## The Serial Console
> +##
> +
> +# To Enable the Serial Console
> +default CONFIG_CONSOLE_SERIAL8250=1
> +
> +## Select the serial console baud rate
> +#default TTYS0_BAUD=115200
> +#default TTYS0_BAUD=57600
> +default TTYS0_BAUD=38400
Why not 115200? If there's a special reason, please document it.
> +#default TTYS0_BAUD=19200
> +#default TTYS0_BAUD=9600
> +#default TTYS0_BAUD=4800
> +#default TTYS0_BAUD=2400
> +#default TTYS0_BAUD=1200
> +
> +# Select the serial console base port
> +default TTYS0_BASE=0x3f8
> +
> +# Select the serial protocol
> +# This defaults to 8 data bits, 1 stop bit, and no parity
> +default TTYS0_LCS=0x3
> +
> +##
> +### Select the linuxBIOS loglevel
> +##
> +## EMERG 1 system is unusable
> +## ALERT 2 action must be taken immediately
> +## CRIT 3 critical conditions
> +## ERR 4 error conditions
> +## WARNING 5 warning conditions
> +## NOTICE 6 normal but significant condition
> +## INFO 7 informational
> +## DEBUG 8 debug-level messages
> +## SPEW 9 Way too many details
> +
> +## Request this level of debugging output
> +default DEFAULT_CONSOLE_LOGLEVEL=5
> +## At a maximum only compile in this level of debugging
> +default MAXIMUM_CONSOLE_LOGLEVEL=5
> +
> +##
> +## Select power on after power fail setting
> +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
> +
> +##
> +## Don't enable the btext console
> +##
> +default CONFIG_CONSOLE_BTEXT=0
> +
> +
> +### End Options.lb
> +end
> Index: LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/auto.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/auto.c
Mising license header.
> @@ -0,0 +1,99 @@
> +#define ASSEMBLY 1
> +#include <stdint.h>
> +#include <device/pci_def.h>
> +#include <arch/io.h>
> +#include <device/pnp_def.h>
> +#include <arch/romcc_io.h>
> +#include <cpu/x86/lapic.h>
> +#include "option_table.h"
> +#include "pc80/mc146818rtc_early.c"
> +#include "pc80/serial.c"
> +#include "arch/i386/lib/console.c"
> +#include "ram/ramtest.c"
> +#include "southbridge/intel/i3100/i3100_early_smbus.c"
> +#include "southbridge/intel/i3100/i3100_early_lpc.c"
> +#include "northbridge/intel/i3100/raminit.h"
> +#include "superio/intel/i3100/i3100.h"
> +#include "cpu/x86/lapic/boot_cpu.c"
> +#include "cpu/x86/mtrr/earlymtrr.c"
> +#include "reset.c"
> +#include "power_reset_check.c"
> +#include "superio/intel/i3100/i3100_early_serial.c"
> +#include "northbridge/intel/i3100/memory_initialized.c"
> +#include "cpu/x86/bist.h"
> +
> +#define SIO_GPIO_BASE 0x680
> +#define SIO_XBUS_BASE 0x4880
> +
> +#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0)
> +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
> +
> +static inline void activate_spd_rom(const struct mem_controller *ctrl)
> +{
> + /* nothing to do */
> +}
> +static inline int spd_read_byte(unsigned device, unsigned address)
Both u16, I think (or was it u8?)
> +{
> + return smbus_read_byte(device, address);
> +}
> +
> +#include "northbridge/intel/i3100/raminit.c"
> +#include "sdram/generic_sdram.c"
> +#include "debug.c"
> +
> +
> +static void main(unsigned long bist)
> +{
> + static const struct mem_controller mch[] = {
> + {
> + .node_id = 0,
> + .f0 = PCI_DEV(0, 0x00, 0),
> + .f1 = PCI_DEV(0, 0x00, 1),
> + .f2 = PCI_DEV(0, 0x00, 2),
> + .f3 = PCI_DEV(0, 0x00, 3),
> + .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
> + .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
> + }
> + };
> +
> + if (bist == 0) {
> + /* Skip this if there was a built in self test failure */
> + early_mtrr_init();
> + if (memory_initialized()) {
> + asm volatile ("jmp __cpu_reset");
> + }
> + }
> + /* Set up the console */
> + i3100_enable_superio();
> + i3100_enable_serial(0x4e, I3100_SP1, TTYS0_BASE);
> + uart_init();
> + console_init();
> +
> + /* Halt if there was a built in self test failure */
> + report_bist_failure(bist);
> +
> +#if 0
> + print_pci_devices();
> +#endif
> + enable_smbus();
> +#if 0
> + dump_spd_registers();
> +#endif
> + power_down_reset_check();
> + sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
ARRAY_SIZE
> +#if 0
> + dump_pci_devices();
> + dump_pci_device(PCI_DEV(0, 0x00, 0));
> + dump_bar14(PCI_DEV(0, 0x00, 0));
> +#endif
> +
> +#if 1
> + ram_check(0x00000000, 0x00100000);
> +#endif
> +
> +#if 0
> + while(1) {
> + hlt();
> + }
> +#endif
> +}
> Index: LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/chip.h
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/chip.h
> @@ -0,0 +1,5 @@
Missing license header.
> +struct chip_operations mainboard_intel_mtarvon_ops;
> +
> +struct mainboard_intel_mtarvon_config {
> + int nothing;
> +};
> Index: LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/cmos.layout
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/cmos.layout
> @@ -0,0 +1,82 @@
> +entries
> +
> +#start-bit length config config-ID name
> +#0 8 r 0 seconds
> +#8 8 r 0 alarm_seconds
> +#16 8 r 0 minutes
> +#24 8 r 0 alarm_minutes
> +#32 8 r 0 hours
> +#40 8 r 0 alarm_hours
> +#48 8 r 0 day_of_week
> +#56 8 r 0 day_of_month
> +#64 8 r 0 month
> +#72 8 r 0 year
> +#80 4 r 0 rate_select
> +#84 3 r 0 REF_Clock
> +#87 1 r 0 UIP
> +#88 1 r 0 auto_switch_DST
> +#89 1 r 0 24_hour_mode
> +#90 1 r 0 binary_values_enable
> +#91 1 r 0 square-wave_out_enable
> +#92 1 r 0 update_finished_enable
> +#93 1 r 0 alarm_interrupt_enable
> +#94 1 r 0 periodic_interrupt_enable
> +#95 1 r 0 disable_clock_updates
> +#96 288 r 0 temporary_filler
> +0 376 r 0 reserved_memory
> +376 1 e 1 power_up_watchdog
> +384 1 e 4 boot_option
> +385 1 e 4 last_boot
> +386 1 e 1 ECC_memory
> +388 4 r 0 reboot_bits
> +392 3 e 5 baud_rate
> +395 1 e 2 hyper_threading
> +397 1 e 1 pxhd_bus_speed_100
> +400 1 e 1 power_on_after_fail
> +412 4 e 6 debug_level
> +416 4 e 7 boot_first
> +420 4 e 7 boot_second
> +424 4 e 7 boot_third
> +428 4 h 0 boot_index
> +432 8 h 0 boot_countdown
> +728 256 h 0 user_data
> +984 16 h 0 check_sum
> +# Reserve the extended AMD configuration registers
> +1000 24 r 0 reserved_memory
> +
> +
> +
> +enumerations
> +
> +#ID value text
> +1 0 Disable
> +1 1 Enable
> +2 0 Enable
> +2 1 Disable
> +4 0 Fallback
> +4 1 Normal
> +5 0 115200
> +5 1 57600
> +5 2 38400
> +5 3 19200
> +5 4 9600
> +5 5 4800
> +5 6 2400
> +5 7 1200
> +6 6 Notice
> +6 7 Info
> +6 8 Debug
> +6 9 Spew
> +7 0 Network
> +7 1 HDD
> +7 2 Floppy
> +7 8 Fallback_Network
> +7 9 Fallback_HDD
> +7 10 Fallback_Floppy
> +#7 3 ROM
> +
> +checksums
> +
> +checksum 392 983 984
> +
> +
> Index: LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/debug.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/debug.c
> @@ -0,0 +1,330 @@
Missing license header.
> +#define SMBUS_MEM_DEVICE_START 0x50
> +#define SMBUS_MEM_DEVICE_END 0x57
> +#define SMBUS_MEM_DEVICE_INC 1
> +
> +static void print_reg(unsigned char index)
> +{
> + unsigned char data;
> +
> + outb(index, 0x2e);
> + data = inb(0x2f);
> + print_debug("0x");
> + print_debug_hex8(index);
> + print_debug(": 0x");
> + print_debug_hex8(data);
> + print_debug("\r\n");
> + return;
Inconsistent coding style.
> +}
> +
> +static void xbus_en(void)
> +{
> + /* select the XBUS function in the SIO */
> + outb(0x07, 0x2e);
> + outb(0x0f, 0x2f);
> + outb(0x30, 0x2e);
> + outb(0x01, 0x2f);
> + return;
> +}
> +
> +static void setup_func(unsigned char func)
> +{
> + /* select the function in the SIO */
> + outb(0x07, 0x2e);
> + outb(func, 0x2f);
0x2e? Didn't you use 0x4e in Config.lb above?
Is this copy-paste code? Is it needed or can we drop it?
> + /* print out the regs */
> + print_reg(0x30);
> + print_reg(0x60);
> + print_reg(0x61);
> + print_reg(0x62);
> + print_reg(0x63);
> + print_reg(0x70);
> + print_reg(0x71);
> + print_reg(0x74);
> + print_reg(0x75);
> + return;
> +}
> +
> +static void siodump(void)
> +{
> + int i;
> + unsigned char data;
> +
> + print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
> + for (i=0x10; i<=0x2d; i++) {
> + print_reg((unsigned char)i);
> + }
> +#if 0
> + print_debug("\r\n*** XBUS REGISTERS ***\r\n");
> + setup_func(0x0f);
> + for (i=0xf0; i<=0xff; i++) {
> + print_reg((unsigned char)i);
> + }
> +
> + print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n");
> + setup_func(0x03);
> + print_reg(0xf0);
> +
> + print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n");
> + setup_func(0x02);
> + print_reg(0xf0);
> +
> +#endif
> + print_debug("\r\n*** GPIO REGISTERS ***\r\n");
> + setup_func(0x07);
> + for (i=0xf0; i<=0xf8; i++) {
> + print_reg((unsigned char)i);
> + }
> + print_debug("\r\n*** GPIO VALUES ***\r\n");
> + data = inb(0x68a);
> + print_debug("\r\nGPDO 4: 0x");
> + print_debug_hex8(data);
> + data = inb(0x68b);
> + print_debug("\r\nGPDI 4: 0x");
> + print_debug_hex8(data);
> + print_debug("\r\n");
> +
> +#if 0
> +
> + print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n");
> + setup_func(0x0a);
> + print_reg(0xf0);
> +
> + print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n");
> + setup_func(0x09);
> + print_reg(0xf0);
> + print_reg(0xf1);
> +
> + print_debug("\r\n*** RTC REGISTERS ***\r\n");
> + setup_func(0x10);
> + print_reg(0xf0);
> + print_reg(0xf1);
> + print_reg(0xf3);
> + print_reg(0xf6);
> + print_reg(0xf7);
> + print_reg(0xfe);
> + print_reg(0xff);
> +
> + print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
> + setup_func(0x14);
> + print_reg(0xf0);
> +#endif
> + return;
> +}
> +
> +static void print_debug_pci_dev(unsigned dev)
> +{
> + print_debug("PCI: ");
> + print_debug_hex8((dev >> 20) & 0xff);
> + print_debug_char(':');
> + print_debug_hex8((dev >> 15) & 0x1f);
> + print_debug_char('.');
> + print_debug_hex8((dev >> 12) & 7);
> +}
> +
> +static void print_pci_devices(void)
> +{
> + device_t dev;
> + for(dev = PCI_DEV(0, 0, 0);
> + dev <= PCI_DEV(0, 0x1f, 0x7);
> + dev += PCI_DEV(0,0,1)) {
> + uint32_t id;
> + id = pci_read_config32(dev, PCI_VENDOR_ID);
> + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
> + (((id >> 16) & 0xffff) == 0xffff) ||
> + (((id >> 16) & 0xffff) == 0x0000)) {
> + continue;
> + }
> + print_debug_pci_dev(dev);
> + print_debug("\r\n");
> + }
> +}
> +
> +static void dump_pci_device(unsigned dev)
> +{
> + int i;
> + print_debug_pci_dev(dev);
> + print_debug("\r\n");
> +
> + for(i = 0; i <= 255; i++) {
> + unsigned char val;
> + if ((i & 0x0f) == 0) {
> + print_debug_hex8(i);
> + print_debug_char(':');
> + }
> + val = pci_read_config8(dev, i);
> + print_debug_char(' ');
> + print_debug_hex8(val);
> + if ((i & 0x0f) == 0x0f) {
> + print_debug("\r\n");
> + }
> + }
> +}
> +
> +static void dump_bar14(unsigned dev)
> +{
> + int i;
> + unsigned long bar;
> +
> + print_debug("BAR 14 Dump\r\n");
> +
> + bar = pci_read_config32(dev, 0x14);
> + for(i = 0; i <= 0x300; i+=4) {
> +#if 0
> + unsigned char val;
> + if ((i & 0x0f) == 0) {
> + print_debug_hex8(i);
> + print_debug_char(':');
> + }
> + val = pci_read_config8(dev, i);
> +#endif
> + if((i%4)==0) {
> + print_debug("\r\n");
> + print_debug_hex16(i);
> + print_debug_char(' ');
> + }
> + print_debug_hex32(read32(bar + i));
> + print_debug_char(' ');
> + }
> + print_debug("\r\n");
> +}
> +
> +static void dump_pci_devices(void)
> +{
> + device_t dev;
> + for(dev = PCI_DEV(0, 0, 0);
> + dev <= PCI_DEV(0, 0x1f, 0x7);
> + dev += PCI_DEV(0,0,1)) {
> + uint32_t id;
> + id = pci_read_config32(dev, PCI_VENDOR_ID);
> + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
> + (((id >> 16) & 0xffff) == 0xffff) ||
> + (((id >> 16) & 0xffff) == 0x0000)) {
> + continue;
> + }
> + dump_pci_device(dev);
> + }
> +}
> +
> +#if 0
> +static void dump_spd_registers(const struct mem_controller *ctrl)
> +{
> + int i;
> + print_debug("\r\n");
> + for(i = 0; i < 4; i++) {
> + unsigned device;
> + device = ctrl->channel0[i];
> + if (device) {
> + int j;
> + print_debug("dimm: ");
> + print_debug_hex8(i);
> + print_debug(".0: ");
> + print_debug_hex8(device);
> + for(j = 0; j < 256; j++) {
> + int status;
> + unsigned char byte;
> + if ((j & 0xf) == 0) {
> + print_debug("\r\n");
> + print_debug_hex8(j);
> + print_debug(": ");
> + }
> + status = smbus_read_byte(device, j);
> + if (status < 0) {
> + print_debug("bad device\r\n");
> + break;
> + }
> + byte = status & 0xff;
> + print_debug_hex8(byte);
> + print_debug_char(' ');
> + }
> + print_debug("\r\n");
> + }
> + device = ctrl->channel1[i];
> + if (device) {
> + int j;
> + print_debug("dimm: ");
> + print_debug_hex8(i);
> + print_debug(".1: ");
> + print_debug_hex8(device);
> + for(j = 0; j < 256; j++) {
> + int status;
> + unsigned char byte;
> + if ((j & 0xf) == 0) {
> + print_debug("\r\n");
> + print_debug_hex8(j);
> + print_debug(": ");
> + }
> + status = smbus_read_byte(device, j);
> + if (status < 0) {
> + print_debug("bad device\r\n");
> + break;
> + }
> + byte = status & 0xff;
> + print_debug_hex8(byte);
> + print_debug_char(' ');
> + }
> + print_debug("\r\n");
> + }
> + }
> +}
> +#endif
> +
> +void dump_spd_registers(void)
> +{
> + unsigned device;
> + device = SMBUS_MEM_DEVICE_START;
> + while(device <= SMBUS_MEM_DEVICE_END) {
> + int status = 0;
> + int i;
> + print_debug("\r\n");
> + print_debug("dimm ");
> + print_debug_hex8(device);
> +
> + for(i = 0; (i < 256) ; i++) {
> + unsigned char byte;
> + if ((i % 16) == 0) {
> + print_debug("\r\n");
> + print_debug_hex8(i);
> + print_debug(": ");
> + }
> + status = smbus_read_byte(device, i);
> + if (status < 0) {
> + print_debug("bad device: ");
> + print_debug_hex8(-status);
> + print_debug("\r\n");
> + break;
> + }
> + print_debug_hex8(status);
> + print_debug_char(' ');
> + }
> + device += SMBUS_MEM_DEVICE_INC;
> + print_debug("\n");
> + }
> +}
> +
> +void dump_ipmi_registers(void)
> +{
> + unsigned device;
> + device = 0x42;
> + while(device <= 0x42) {
> + int status = 0;
> + int i;
> + print_debug("\r\n");
> + print_debug("ipmi ");
> + print_debug_hex8(device);
> +
> + for(i = 0; (i < 8) ; i++) {
> + unsigned char byte;
> + status = smbus_read_byte(device, 2);
> + if (status < 0) {
> + print_debug("bad device: ");
> + print_debug_hex8(-status);
> + print_debug("\r\n");
> + break;
> + }
> + print_debug_hex8(status);
> + print_debug_char(' ');
> + }
> + device += SMBUS_MEM_DEVICE_INC;
> + print_debug("\n");
> + }
> +}
> Index: LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/failover.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/failover.c
Missing license header.
> @@ -0,0 +1,46 @@
> +#define ASSEMBLY 1
> +#include <stdint.h>
> +#include <device/pci_def.h>
> +#include <device/pci_ids.h>
> +#include <arch/io.h>
> +#include <arch/romcc_io.h>
> +#include <cpu/x86/lapic.h>
> +#include "pc80/serial.c"
> +#include "arch/i386/lib/console.c"
> +#include "pc80/mc146818rtc_early.c"
> +#include "cpu/x86/lapic/boot_cpu.c"
> +#include "northbridge/intel/i3100/memory_initialized.c"
> +
> +static unsigned long main(unsigned long bist)
> +{
> + /* Did just the cpu reset? */
> + if (memory_initialized()) {
> + if (last_boot_normal()) {
> + goto normal_image;
> + } else {
> + goto cpu_reset;
> + }
> + }
> +
> + /* This is the primary cpu how should I boot? */
> + else if (do_normal_boot()) {
> + goto normal_image;
> + }
> + else {
> + goto fallback_image;
> + }
> + normal_image:
> + asm volatile ("jmp __normal_image"
> + : /* outputs */
> + : "a" (bist) /* inputs */
> + : /* clobbers */
> + );
> + cpu_reset:
> + asm volatile ("jmp __cpu_reset"
> + : /* outputs */
> + : "a"(bist) /* inputs */
> + : /* clobbers */
> + );
> + fallback_image:
> + return bist;
> +}
> Index: LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/irq_tables.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/irq_tables.c
> @@ -0,0 +1,24 @@
Missing license header.
> +#include <arch/pirq_routing.h>
> +
> +const struct irq_routing_table intel_irq_routing_table = {
> + PIRQ_SIGNATURE, /* u32 signature */
> + PIRQ_VERSION, /* u16 version */
> + 48, /* u16 Table size 32+(16*devices) */
Leave it at 32+16*IRQ_SLOT_COUNT please.
> + 0x00, /* u8 Bus 0 */
> + 0xf8, /* u8 Device 1f, Function 0 */
(0x1f << 3) | 0x0,
> + 0x0000, /* u16 reserve IRQ for PCI */
> + 0x8086, /* u16 Vendor */
> + 0x2670, /* Device ID */
> + 0x00000000, /* u32 miniport_data */
> + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
> + 0x49, /* u8 checksum - mod 256 checksum must give zero */
> + { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
> + {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
> + }
> +};
> +
> +unsigned long write_pirq_routing_table(unsigned long addr)
> +{
> + return copy_pirq_routing_table(addr);
> +}
> +
> Index: LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/mainboard.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/mainboard.c
> @@ -0,0 +1,7 @@
Missing license header.
> +#include <device/device.h>
> +#include "chip.h"
> +
> +struct chip_operations mainboard_intel_mtarvon_ops = {
> + CHIP_NAME("Intel MtArvon Mainboard")
CHIP_NAME("Intel Mt. Arvon Mainboard")
> +};
> +
> Index: LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/microcode_updates.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/microcode_updates.c
> @@ -0,0 +1,1563 @@
> +/* WARNING - Intel has a new data structure that has variable length
> + * microcode update lengths. They are encoded in int 8 and 9. A
> + * dummy header of nulls must terminate the list.
> + */
> +
> +static const unsigned int microcode_updates[] __attribute__ ((aligned(16))) = {
> + /*
> + Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
> + These microcode updates are distributed for the sole purpose of
> + installation in the BIOS or Operating System of computer systems
> + which include an Intel P6 family microprocessor sold or distributed
> + to or by you. You are authorized to copy and install this material
> + on such systems. You are not authorized to use this material for
> + any other purpose.
> + */
The copyright header should be at the top of the file.
What's the original source of this file? URL?
Also, please check the microcode update patches from Corey, this will
likely need some changes / merging when those get committed.
> +
> + /* M1DF340E.TXT - Noconoa D-0 */
> +
> +
> + 0x00000001, /* Header Version */
> + 0x0000000e, /* Patch ID */
> + 0x05042004, /* DATE */
> + 0x00000f34, /* CPUID */
> + 0x9b18561d, /* Checksum */
> + 0x00000001, /* Loader Version */
> + 0x0000001d, /* Platform ID */
> + 0x000017d0, /* Data size */
> + 0x00001800, /* Total size */
> + 0x00000000, /* reserved */
> + 0x00000000, /* reserved */
> + 0x00000000, /* reserved */
> + 0x9fbf327a,
[...]
> + 0x0f06b850,
> +/* Dummy terminator */
> + 0x0, 0x0, 0x0, 0x0,
> + 0x0, 0x0, 0x0, 0x0,
> + 0x0, 0x0, 0x0, 0x0,
> + 0x0, 0x0, 0x0, 0x0,
> +};
> +
> +
> Index: LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/mptable.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/mptable.c
Missing license header.
> @@ -0,0 +1,143 @@
> +#include <console/console.h>
> +#include <arch/smp/mpspec.h>
> +#include <device/pci.h>
> +#include <string.h>
> +#include <stdint.h>
> +
> +void *smp_write_config_table(void *v)
> +{
> + static const char sig[4] = "PCMP";
> + static const char oem[8] = "Intel ";
> + static const char productid[12] = "MtArvon ";
static const char productid[12] = "Mt. Arvon ";
(unless the original firmware used "MtArvon" everywhere consistently)
> + struct mp_config_table *mc;
> + unsigned char bus_isa = 7;
> + unsigned char bus_pci = 6;
> + unsigned char bus_pcie_a = 1;
> +
> + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
> + memset(mc, 0, sizeof(*mc));
> +
> + memcpy(mc->mpc_signature, sig, sizeof(sig));
> + mc->mpc_length = sizeof(*mc); /* initially just the header */
> + mc->mpc_spec = 0x04;
> + mc->mpc_checksum = 0; /* not yet computed */
> + memcpy(mc->mpc_oem, oem, sizeof(oem));
> + memcpy(mc->mpc_productid, productid, sizeof(productid));
> + mc->mpc_oemptr = 0;
> + mc->mpc_oemsize = 0;
> + mc->mpc_entry_count = 0; /* No entries yet... */
> + mc->mpc_lapic = LAPIC_ADDR;
> + mc->mpe_length = 0;
> + mc->mpe_checksum = 0;
> + mc->reserved = 0;
> +
> + smp_write_processors(mc);
> +
> + /* define bus and isa numbers */
> + smp_write_bus(mc, 0, "PCI ");
> + smp_write_bus(mc, bus_pci, "PCI ");
> + smp_write_bus(mc, bus_pcie_a, "PCI ");
> + smp_write_bus(mc, bus_isa, "ISA ");
> +
> + /* IOAPIC handling */
> +
> + smp_write_ioapic(mc, 0x01, 0x20, 0xfec00000);
> +
> + /* ISA backward compatibility interrupts */
> + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
> + bus_isa, 0x00, 0x01, 0x00);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
> + bus_isa, 0x01, 0x01, 0x01);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
> + bus_isa, 0x00, 0x01, 0x02);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
> + bus_isa, 0x03, 0x01, 0x03);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
> + bus_isa, 0x04, 0x01, 0x04);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
> + bus_isa, 0x06, 0x01, 0x06);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
> + bus_isa, 0x08, 0x01, 0x08);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
> + bus_isa, 0x09, 0x01, 0x09);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
> + bus_isa, 0x0c, 0x01, 0x0c);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
> + bus_isa, 0x0d, 0x01, 0x0d);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
> + bus_isa, 0x0e, 0x01, 0x0e);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
> + bus_isa, 0x0f, 0x01, 0x0f);
> +
> + /* Standard local interrupt assignments */
> + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
> + bus_isa, 0x00, MP_APIC_ALL, 0x00);
> + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
> + bus_isa, 0x00, MP_APIC_ALL, 0x01);
> +
> + /* Internal PCI devices */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + 0, (0x01<<2)|0, 0x01, 0x10); /* DMA controller */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + 0, (0x02<<2)|0, 0x01, 0x10); /* PCIe port A */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + 0, (0x03<<2)|0, 0x01, 0x10); /* PCIe port A1 */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + 0, (0x1c<<2)|0, 0x01, 0x10); /* PCIe port B0 */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + 0, (0x1c<<2)|1, 0x01, 0x11); /* PCIe port B1 */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + 0, (0x1c<<2)|2, 0x01, 0x12); /* PCIe port B2 */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + 0, (0x1c<<2)|3, 0x01, 0x13); /* PCIe port B3 */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + 0, (0x1d<<2)|0, 0x01, 0x10); /* UHCI0/EHCI */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + 0, (0x1d<<2)|1, 0x01, 0x11); /* UHCI1 */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + 0, (0x1e<<2)|0, 0x01, 0x10); /* Audio */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + 0, (0x1e<<2)|1, 0x01, 0x11); /* Modem */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + 0, (0x1f<<2)|1, 0x01, 0x11); /* SATA/SMBus */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + 0, (0x1f<<2)|3, 0x01, 0x13); /* ? */
> +
> + /* PCI slot */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + bus_pci, 0x00, 0x01, 0x10);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + bus_pci, 0x01, 0x01, 0x11);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + bus_pci, 0x02, 0x01, 0x12);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + bus_pci, 0x03, 0x01, 0x13);
> +
> + /* PCIe port A slot */
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + bus_pcie_a, 0x00, 0x01, 0x10);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + bus_pcie_a, 0x01, 0x01, 0x11);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + bus_pcie_a, 0x02, 0x01, 0x12);
> + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
> + bus_pcie_a, 0x03, 0x01, 0x13);
> +
> + /* There is no extension information... */
> +
> + /* Compute the checksums */
> + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
> +
> + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
> + printk_debug("Wrote the mp table end at: %p - %p\n",
> + mc, smp_next_mpe_entry(mc));
> + return smp_next_mpe_entry(mc);
> +}
> +
> +unsigned long write_smp_table(unsigned long addr)
> +{
> + void *v;
> + v = smp_write_floating_table(addr);
> + return (unsigned long)smp_write_config_table(v);
> +}
> +
> Index: LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/power_reset_check.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/power_reset_check.c
Missing license header.
> @@ -0,0 +1,12 @@
> +
> +static void power_down_reset_check(void)
> +{
> + uint8_t cmos;
> +
> + cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
> + print_debug("Boot byte = ");
> + print_debug_hex8(cmos);
> + print_debug("\r\n");
> +
> + if((cmos>2)&&(cmos&1)) full_reset();
Please fix the coding style, see
http://www.coreboot.org/Development_Guidelines#Coding_Style
> +}
> Index: LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/reset.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/mainboard/intel/mtarvon/reset.c
Missing license header.
I haven't yet checked how many changes each of those files have compared
to what you used as a basis. If possible please base your code on
something which already has the proper license headers, that's easier.
Otherwise you'll have to research the origins of the files and who's the
copyright holder of the code, and which license is used (if unknown you
have to assume GPLv2-only).
> @@ -0,0 +1,40 @@
> +#include <arch/io.h>
> +#include <device/pci_def.h>
> +#include <device/pci_ids.h>
> +#ifndef __ROMCC__
> +#include <device/device.h>
> +#define PCI_ID(VENDOR_ID, DEVICE_ID) \
> + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
> +#define PCI_DEV_INVALID 0
> +
> +static inline device_t pci_locate_device(unsigned pci_id, device_t from)
> +{
> + return dev_find_device(pci_id >> 16, pci_id & 0xffff, from);
> +}
> +#endif
> +
> +void soft_reset(void)
> +{
> + outb(0x04, 0xcf9);
> +}
> +void hard_reset(void)
> +{
> + outb(0x02, 0xcf9);
> + outb(0x06, 0xcf9);
> +}
> +void full_reset(void)
> +{
> + device_t dev;
> + /* Enable power on after power fail... */
> + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_ISA), 0);
Maybe rename *_ISA to *_LPC? I think it's LPC, correct?
> + if (dev != PCI_DEV_INVALID) {
> + unsigned byte;
> + byte = pci_read_config8(dev, 0xa4);
> + byte &= 0xfe;
> + pci_write_config8(dev, 0xa4, byte);
> +
> + }
> + outb(0x0e, 0xcf9);
> +}
> +
> +
> Index: LinuxBIOSv2-3023/src/southbridge/intel/i3100/Config.lb
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/southbridge/intel/i3100/Config.lb
Missing license header.
> @@ -0,0 +1,8 @@
> +config chip.h
> +driver i3100.o
> +driver i3100_uhci.o
> +driver i3100_lpc.o
> +driver i3100_sata.o
> +driver i3100_ehci.o
> +driver i3100_smbus.o
> +driver i3100_pci.o
> Index: LinuxBIOSv2-3023/src/southbridge/intel/i3100/chip.h
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/southbridge/intel/i3100/chip.h
> @@ -0,0 +1,30 @@
Missing license header.
> +struct southbridge_intel_i3100_config
> +{
> +#define I3100_GPIO_USE_MASK 0x03
> +#define I3100_GPIO_USE_DEFAULT 0x00
> +#define I3100_GPIO_USE_AS_NATIVE 0x01
> +#define I3100_GPIO_USE_AS_GPIO 0x02
> +
> +#define I3100_GPIO_SEL_MASK 0x0c
> +#define I3100_GPIO_SEL_DEFAULT 0x00
> +#define I3100_GPIO_SEL_OUTPUT 0x04
> +#define I3100_GPIO_SEL_INPUT 0x08
> +
> +#define I3100_GPIO_LVL_MASK 0x30
> +#define I3100_GPIO_LVL_DEFAULT 0x00
> +#define I3100_GPIO_LVL_LOW 0x10
> +#define I3100_GPIO_LVL_HIGH 0x20
> +#define I3100_GPIO_LVL_BLINK 0x30
> +
> +#define I3100_GPIO_INV_MASK 0xc0
> +#define I3100_GPIO_INV_DEFAULT 0x00
> +#define I3100_GPIO_INV_OFF 0x40
> +#define I3100_GPIO_INV_ON 0x80
> +
> + /* GPIO use select */
> + unsigned char gpio[64];
> + unsigned int pirq_a_d;
> + unsigned int pirq_e_h;
Use u16 etc, please.
> +};
> +extern struct chip_operations southbridge_intel_i3100_ops;
> +
> Index: LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100.c
> @@ -0,0 +1,48 @@
Missing license header.
> +#include <console/console.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <device/pci_ids.h>
> +#include "i3100.h"
> +
> +void i3100_enable(device_t dev)
> +{
> + device_t lpc_dev;
> + unsigned index = 0;
> + uint16_t reg_old, reg;
> +
> + /* See if we are behind the 3100 pci bridge */
> + lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
> + if((dev->path.u.pci.devfn &0xf8)== 0xf8) {
> + index = dev->path.u.pci.devfn & 7;
> + }
> + else if((dev->path.u.pci.devfn &0xf8)== 0xe8) {
> + index = (dev->path.u.pci.devfn & 7) +8;
> + }
> + if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) {
> + return;
> + }
> + if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
> + (lpc_dev->device != PCI_DEVICE_ID_INTEL_3100_ISA)) {
> + uint32_t id;
> + id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
> + if (id != (PCI_VENDOR_ID_INTEL |
> + (PCI_DEVICE_ID_INTEL_3100_ISA << 16))) {
> + return;
> + }
> + }
> +
> + reg = reg_old = pci_read_config16(lpc_dev, 0xf2);
> + reg &= ~(1 << index);
> + if (!dev->enabled) {
> + reg |= (1 << index);
> + }
> + if (reg != reg_old) {
> + pci_write_config16(lpc_dev, 0xf2, reg);
> + }
Coding style issues, but looks good otherwise. Didn't check the
datasheet yet, though.
> +
> +}
> +
> +struct chip_operations southbridge_intel_i3100_ops = {
> + CHIP_NAME("Intel 3100 Southbridge")
> + .enable_dev = i3100_enable,
> +};
> Index: LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100.h
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100.h
Missing license header.
> @@ -0,0 +1,7 @@
> +#ifndef I3100_H
> +#define I3100_H
SOUTHBRIDGE_INTEL_I3100_I3100_H
> +#include "chip.h"
> +
> +void i3100_enable(device_t dev);
> +
> +#endif /* I3100 */
Ditto.
> Index: LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_early_smbus.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_early_smbus.c
> @@ -0,0 +1,107 @@
Missing license header.
> +#include "i3100_smbus.h"
> +
> +#define SMBUS_IO_BASE 0x0f00
> +
> +static void enable_smbus(void)
> +{
> + device_t dev;
> + dev = pci_locate_device(PCI_ID(0x8086, 0x269b), 0);
> + if (dev == PCI_DEV_INVALID) {
> + die("SMBUS controller not found\r\n");
> + }
> + uint8_t enable;
> + print_spew("SMBus controller enabled\r\n");
> + pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
> + pci_write_config8(dev, 0x40, 1);
> + pci_write_config8(dev, 0x4, 1);
> + /* SMBALERT_DIS */
> + outb(4, SMBUS_IO_BASE + SMBSLVCMD);
> +
> + /* Disable interrupt generation */
> + outb(0, SMBUS_IO_BASE + SMBHSTCTL);
> + dev = pci_locate_device(PCI_ID(0x8086, 0x2670), 0);
> + if (dev == PCI_DEV_INVALID) {
> + die("ISA bridge not found\r\n");
> + }
Is this last part required? Drop?
> +}
> +
> +static int smbus_read_byte(unsigned device, unsigned address)
> +{
> + return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
> +}
> +
> +static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
> +{
> + if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
> + return;
> + }
> + return;
> +}
> +
> +static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
> + unsigned data1, unsigned data2)
> +{
> + unsigned char global_control_register;
> + unsigned char global_status_register;
> + unsigned char byte;
> + unsigned char stat;
u8
> + int i;
> +
> + /* chear the PM timeout flags, SECOND_TO_STS */
> + outw(inw(0x0400 + 0x66), 0x0400 + 0x66);
Magic constants, maybe use #defines here?
> +
> + if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
> + return -2;
> + }
> +
> + /* setup transaction */
> + /* Obtain ownership */
> + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
> + for(stat=0;(stat&0x40)==0;) {
> + stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
> + }
> + /* clear the done bit */
> + outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
> + /* disable interrupts */
> + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
> +
> + /* set the device I'm talking too */
> + outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
> +
> + /* set the command address */
> + outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
> +
> + /* set the block length */
> + outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0);
> +
> + /* try sending out the first byte of data here */
> + byte=(data1>>(0))&0x0ff;
> + outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
> + /* issue a block write command */
> + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
> + SMBUS_IO_BASE + SMBHSTCTL);
> +
> + for(i=0;i<length;i++) {
> +
> + /* poll for transaction completion */
> + if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
> + return -3;
> + }
> +
> + /* load the next byte */
> + if(i>3)
> + byte=(data2>>(i%4))&0x0ff;
> + else
> + byte=(data1>>(i))&0x0ff;
> + outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
> +
> + /* clear the done bit */
> + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
> + SMBUS_IO_BASE + SMBHSTSTAT);
> + }
> +
> + print_debug("SMBUS Block complete\r\n");
> + return 0;
> +}
> +
> Index: LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_ehci.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_ehci.c
Missing license header.
> @@ -0,0 +1,50 @@
> +#include <console/console.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <device/pci_ids.h>
> +#include <device/pci_ops.h>
> +#include "i3100.h"
> +
> +static void ehci_init(struct device *dev)
> +{
> + uint32_t cmd;
> +
> + printk_debug("EHCI: Setting up controller.. ");
> + cmd = pci_read_config32(dev, PCI_COMMAND);
> + pci_write_config32(dev, PCI_COMMAND,
> + cmd | PCI_COMMAND_MASTER);
> +
> + printk_debug("done.\n");
> +}
> +
> +static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
> +{
> + uint8_t access_cntl;
> + access_cntl = pci_read_config8(dev, 0x80);
> + /* Enable writes to protected registers */
> + pci_write_config8(dev, 0x80, access_cntl | 1);
> + /* Write the subsystem vendor and device id */
> + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
> + ((device & 0xffff) << 16) | (vendor & 0xffff));
> + /* Restore protection */
> + pci_write_config8(dev, 0x80, access_cntl);
> +}
> +
> +static struct pci_operations lops_pci = {
> + .set_subsystem = &ehci_set_subsystem,
> +};
> +static struct device_operations ehci_ops = {
> + .read_resources = pci_dev_read_resources,
> + .set_resources = pci_dev_set_resources,
> + .enable_resources = pci_dev_enable_resources,
> + .init = ehci_init,
> + .scan_bus = 0,
> + .enable = i3100_enable,
> + .ops_pci = &lops_pci,
> +};
> +
> +static struct pci_driver ehci_driver __pci_driver = {
> + .ops = &ehci_ops,
> + .vendor = PCI_VENDOR_ID_INTEL,
> + .device = PCI_DEVICE_ID_INTEL_3100_EHCI,
> +};
> Index: LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_lpc.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_lpc.c
> @@ -0,0 +1,296 @@
> +/*
> + * (C) 2004 Linux Networx
> + */
Missing license header.
If nontrivial amounts of the code is still from Linux Networx, keep the
copyright line (and add yours), but add the GPL header. GPLv2-only for
all Linux Networx code btw. (not GPLv2-or-later).
> +#include <console/console.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <device/pci_ids.h>
> +#include <device/pci_ops.h>
> +#include <pc80/mc146818rtc.h>
> +#include <pc80/isa-dma.h>
> +#include <arch/io.h>
> +#include "i3100.h"
> +
> +#define ACPI_BAR 0x40
> +#define GPIO_BAR 0x48
> +#define RCBA 0xf0
> +
> +#define NMI_OFF 0
> +#define MAINBOARD_POWER_OFF 0
> +#define MAINBOARD_POWER_ON 1
> +
> +#ifndef MAINBOARD_POWER_ON_AFTER_FAIL
> +#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON
> +#endif
> +
> +#define ALL (0xff << 24)
> +#define NONE (0)
> +#define DISABLED (1 << 16)
> +#define ENABLED (0 << 16)
> +#define TRIGGER_EDGE (0 << 15)
> +#define TRIGGER_LEVEL (1 << 15)
> +#define POLARITY_HIGH (0 << 13)
> +#define POLARITY_LOW (1 << 13)
> +#define PHYSICAL_DEST (0 << 11)
> +#define LOGICAL_DEST (1 << 11)
> +#define ExtINT (7 << 8)
> +#define NMI (4 << 8)
> +#define SMI (2 << 8)
> +#define INT (1 << 8)
> +
> +static void setup_ioapic(device_t dev)
> +{
> + int i;
> + uint32_t value_low, value_high;
> + uint32_t ioapic_base = 0xfec00000;
> + volatile uint32_t *l;
> + uint32_t interrupts;
> + struct resource *res;
> +
> + /* Enable IO APIC */
> + res = find_resource(dev, RCBA);
> + if (!res) {
> + return;
> + }
> + *((uint8_t *)(res->base + 0x31ff)) |= (1 << 0);
> +
> + l = (uint32_t *) ioapic_base;
> +
> + l[0] = 0x01;
> + interrupts = (l[04] >> 16) & 0xff;
> + for (i = 0; i < interrupts; i++) {
> + l[0] = (i * 2) + 0x10;
> + l[4] = DISABLED;
> + value_low = l[4];
> + l[0] = (i * 2) + 0x11;
> + l[4] = NONE; /* Should this be an address? */
> + value_high = l[4];
> + if (value_low == 0xffffffff) {
> + printk_warning("%d IO APIC not responding.\n",
> + dev_path(dev));
> + return;
> + }
> + }
> +
> + /* Put the APIC in virtual wire mode */
> + l[0] = 0x10;
> + l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
> +}
> +
> +#define SERIRQ_CNTL 0x64
> +static void i3100_enable_serial_irqs(device_t dev)
> +{
> + /* set packet length and toggle silent mode bit */
> + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
> + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0));
> +}
> +
> +typedef struct southbridge_intel_i3100_config config_t;
> +
> +static void set_i3100_gpio_use_sel(
> + device_t dev, struct resource *res, config_t *config)
> +{
> + uint32_t gpio_use_sel, gpio_use_sel2;
> + int i;
> +
> + gpio_use_sel = 0x1b0ce7c3;
> + gpio_use_sel2 = 0x00000107;
> + outl(gpio_use_sel, res->base + 0x00);
> + outl(gpio_use_sel2, res->base + 0x30);
> +}
> +
> +static void set_i3100_gpio_direction(
> + device_t dev, struct resource *res, config_t *config)
> +{
> + uint32_t gpio_io_sel, gpio_io_sel2;
> + int i;
> +
> + gpio_io_sel = 0xed00ffff;
> + gpio_io_sel2 = 0x00000307;
> + outl(gpio_io_sel, res->base + 0x04);
> + outl(gpio_io_sel2, res->base + 0x34);
> +}
> +
> +static void set_i3100_gpio_level(
> + device_t dev, struct resource *res, config_t *config)
> +{
> + uint32_t gpio_lvl, gpio_lvl2;
> + uint32_t gpio_blink;
> + int i;
> +
> + gpio_lvl = 0x00030000;
> + gpio_blink = 0x00000000;
> + gpio_lvl2 = 0x00000300;
> + outl(gpio_lvl, res->base + 0x0c);
> + outl(gpio_blink, res->base + 0x18);
> + outl(gpio_lvl2, res->base + 0x38);
> +}
> +
> +static void set_i3100_gpio_inv(
> + device_t dev, struct resource *res, config_t *config)
> +{
> + uint32_t gpio_inv;
> + int i;
> +
> + gpio_inv = 0x00006000;
> + outl(gpio_inv, res->base + 0x2c);
> +}
> +
> +static void i3100_pirq_init(device_t dev)
> +{
> + config_t *config;
> +
> + /* Get the chip configuration */
> + config = dev->chip_info;
> +
> + if(config->pirq_a_d) {
> + pci_write_config32(dev, 0x60, config->pirq_a_d);
> + }
> + if(config->pirq_e_h) {
> + pci_write_config32(dev, 0x68, config->pirq_e_h);
> + }
> +}
> +
> +
> +static void i3100_gpio_init(device_t dev)
> +{
> + struct resource *res;
> + config_t *config;
> +
> + /* Skip if I don't have any configuration */
> + if (!dev->chip_info) {
> + return;
> + }
> + /* The programmer is responsible for ensuring
> + * a valid gpio configuration.
> + */
> +
> + /* Get the chip configuration */
> + config = dev->chip_info;
> + /* Find the GPIO bar */
> + res = find_resource(dev, GPIO_BAR);
> + if (!res) {
> + return;
> + }
> +
> + /* Set the use selects */
> + set_i3100_gpio_use_sel(dev, res, config);
> +
> + /* Set the IO direction */
> + set_i3100_gpio_direction(dev, res, config);
> +
> + /* Setup the input inverters */
> + set_i3100_gpio_inv(dev, res, config);
> +
> + /* Set the value on the GPIO output pins */
> + set_i3100_gpio_level(dev, res, config);
> +
> +}
> +
> +
> +static void lpc_init(struct device *dev)
> +{
> + uint8_t byte;
> + uint32_t value;
> + int pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL;
> +
> + setup_ioapic(dev);
> +
> + /* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
> + pci_write_config32(dev, 0xd0, 0x00000000);
> +
> + i3100_enable_serial_irqs(dev);
> +
> + get_option(&pwr_on, "power_on_after_fail");
> + byte = pci_read_config8(dev, 0xa4);
> + byte &= 0xfe;
> + if (!pwr_on) {
> + byte |= 1;
> + }
> + pci_write_config8(dev, 0xa4, byte);
> + printk_info("set power %s after power fail\n", pwr_on?"on":"off");
> +
> + /* Set up the PIRQ */
> + i3100_pirq_init(dev);
> +
> + /* Set the state of the gpio lines */
> + i3100_gpio_init(dev);
> +
> + /* Initialize the real time clock */
> + rtc_init(0);
> +
> + /* Initialize isa dma */
> + isa_dma_init();
> +}
> +
> +static void i3100_lpc_read_resources(device_t dev)
> +{
> + struct resource *res;
> +
> + /* Get the normal pci resources of this device */
> + pci_dev_read_resources(dev);
> +
> + /* Add the ACPI BAR */
> + res = pci_get_resource(dev, ACPI_BAR);
> +
> + /* Add the GPIO BAR */
> + res = pci_get_resource(dev, GPIO_BAR);
> +
> + /* Add an extra subtractive resource for both memory and I/O */
> + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
> + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
> +
> + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
> + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
> +
> + /* Add resource for RCBA */
> + res = new_resource(dev, RCBA);
> + res->size = 0x4000;
> + res->limit = 0xffffc000;
> + res->align = 14;
> + res->gran = 14;
> + res->flags = IORESOURCE_MEM;
> +}
> +
> +static void i3100_lpc_enable_resources(device_t dev)
> +{
> + uint8_t acpi_cntl, gpio_cntl;
> +
> + /* Enable the normal pci resources */
> + pci_dev_enable_resources(dev);
> +
> + /* Enable the ACPI bar */
> + acpi_cntl = pci_read_config8(dev, 0x44);
> + acpi_cntl |= (1 << 4);
> + pci_write_config8(dev, 0x44, acpi_cntl);
> +
> + /* Enable the GPIO bar */
> + gpio_cntl = pci_read_config8(dev, 0x4c);
> + gpio_cntl |= (1 << 4);
> + pci_write_config8(dev, 0x4c, gpio_cntl);
> +
> + /* Enable the RCBA */
> + pci_write_config32(dev, RCBA, pci_read_config32(dev, RCBA) | (1 << 0));
> +
> + enable_childrens_resources(dev);
> +}
> +
> +static struct pci_operations lops_pci = {
> + .set_subsystem = 0,
> +};
> +
> +static struct device_operations lpc_ops = {
> + .read_resources = i3100_lpc_read_resources,
> + .set_resources = pci_dev_set_resources,
> + .enable_resources = i3100_lpc_enable_resources,
> + .init = lpc_init,
> + .scan_bus = scan_static_bus,
> + .enable = i3100_enable,
> + .ops_pci = &lops_pci,
> +};
> +
> +static struct pci_driver lpc_driver __pci_driver = {
> + .ops = &lpc_ops,
> + .vendor = PCI_VENDOR_ID_INTEL,
> + .device = PCI_DEVICE_ID_INTEL_3100_ISA,
> +};
> Index: LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_pci.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_pci.c
> @@ -0,0 +1,37 @@
Missing license header.
Trivial enough to only use your coypright line (IMHO), no need for lengthy
svn history research here.
> +#include <console/console.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <device/pci_ids.h>
> +#include <device/pci_ops.h>
> +#include "i3100.h"
> +
> +static void pci_init(struct device *dev)
> +{
> +
> + uint16_t word;
> +
> + /* Clear system errors */
> + word = pci_read_config16(dev, 0x06);
> + word |= 0xf900; /* Clear possible errors */
> + pci_write_config16(dev, 0x06, word);
> +
> + word = pci_read_config16(dev, 0x1e);
> + word |= 0xf800; /* Clear possible errors */
> + pci_write_config16(dev, 0x1e, word);
> +}
> +
> +static struct device_operations pci_ops = {
> + .read_resources = pci_bus_read_resources,
> + .set_resources = pci_dev_set_resources,
> + .enable_resources = pci_bus_enable_resources,
> + .init = pci_init,
> + .scan_bus = pci_scan_bridge,
> + .ops_pci = 0,
> +};
> +
> +static struct pci_driver pci_driver __pci_driver = {
> + .ops = &pci_ops,
> + .vendor = PCI_VENDOR_ID_INTEL,
> + .device = PCI_DEVICE_ID_INTEL_3100_PCI,
> +};
> +
> Index: LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_sata.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_sata.c
> @@ -0,0 +1,67 @@
Missing license header.
> +#include <console/console.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <device/pci_ids.h>
> +#include <device/pci_ops.h>
> +#include "i3100.h"
> +
> +static void sata_init(struct device *dev)
> +{
> + /* Enable SATA devices */
> +
> + printk_debug("SATA init\n");
> + /* SATA configuration */
> + pci_write_config8(dev, 0x04, 0x07);
> + pci_write_config8(dev, 0x09, 0x8f);
> +
> + /* Set timings */
> + pci_write_config16(dev, 0x40, 0x0a307);
> + pci_write_config16(dev, 0x42, 0x0a307);
> +
> + /* Sync DMA */
> + pci_write_config16(dev, 0x48, 0x000f);
> + pci_write_config16(dev, 0x4a, 0x1111);
> +
> + /* Fast ATA */
> + pci_write_config16(dev, 0x54, 0x1000);
> +
> + /* Select IDE mode */
> + pci_write_config8(dev, 0x90, 0x00);
> +
> + /* Enable ports 0-3 */
> + pci_write_config8(dev, 0x92, 0x0f);
> +
> + printk_debug("SATA Enabled\n");
> +}
> +
> +static void i3100_sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
> +{
> + /* This value is also visible in usb1, usb2 and smbus functions */
> + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
> + ((device & 0xffff) << 16) | (vendor & 0xffff));
> +}
> +
> +static struct pci_operations lops_pci = {
> + .set_subsystem = i3100_sata_set_subsystem,
> +};
> +static struct device_operations sata_ops = {
> + .read_resources = pci_dev_read_resources,
> + .set_resources = pci_dev_set_resources,
> + .enable_resources = pci_dev_enable_resources,
> + .init = sata_init,
> + .scan_bus = 0,
> + .ops_pci = &lops_pci,
> +};
> +
> +static struct pci_driver sata_driver __pci_driver = {
> + .ops = &sata_ops,
> + .vendor = PCI_VENDOR_ID_INTEL,
> + .device = PCI_DEVICE_ID_INTEL_3100_SATA,
> +};
> +
> +static struct pci_driver sata_driver_nr __pci_driver = {
> + .ops = &sata_ops,
> + .vendor = PCI_VENDOR_ID_INTEL,
> + .device = PCI_DEVICE_ID_INTEL_3100_SATA_R,
> +};
> +
> Index: LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_smbus.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_smbus.c
> @@ -0,0 +1,45 @@
Missing license header.
> +#include <device/device.h>
> +#include <device/path.h>
> +#include <device/pci.h>
> +#include <device/pci_ids.h>
> +#include <device/pci_ops.h>
> +#include <device/smbus.h>
> +#include <arch/io.h>
> +#include "i3100.h"
> +#include "i3100_smbus.h"
> +
> +static int lsmbus_read_byte(struct bus *bus, device_t dev, uint8_t address)
> +{
> + unsigned device;
> + struct resource *res;
> +
> + device = dev->path.u.i2c.device;
> + res = find_resource(bus->dev, 0x20);
> +
> + return do_smbus_read_byte(res->base, device, address);
> +}
> +
> +static struct smbus_bus_operations lops_smbus_bus = {
> + .read_byte = lsmbus_read_byte,
> +};
> +static struct pci_operations lops_pci = {
> + /* The subsystem id follows the ide controller */
> + .set_subsystem = 0,
> +};
> +static struct device_operations smbus_ops = {
> + .read_resources = pci_dev_read_resources,
> + .set_resources = pci_dev_set_resources,
> + .enable_resources = pci_dev_enable_resources,
> + .init = 0,
> + .scan_bus = scan_static_bus,
> + .enable = i3100_enable,
> + .ops_pci = &lops_pci,
> + .ops_smbus_bus = &lops_smbus_bus,
> +};
> +
> +static struct pci_driver smbus_driver __pci_driver = {
> + .ops = &smbus_ops,
> + .vendor = PCI_VENDOR_ID_INTEL,
> + .device = PCI_DEVICE_ID_INTEL_3100_SMB,
> +};
> +
> Index: LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_smbus.h
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_smbus.h
> @@ -0,0 +1,106 @@
Missing license header.
> +#include <device/smbus_def.h>
> +
> +#define SMBHSTSTAT 0x0
> +#define SMBHSTCTL 0x2
> +#define SMBHSTCMD 0x3
> +#define SMBXMITADD 0x4
> +#define SMBHSTDAT0 0x5
> +#define SMBHSTDAT1 0x6
> +#define SMBBLKDAT 0x7
> +#define SMBTRNSADD 0x9
> +#define SMBSLVDATA 0xa
> +#define SMLINK_PIN_CTL 0xe
> +#define SMBUS_PIN_CTL 0xf
> +#define SMBSLVCMD 0x11
> +
> +#define SMBUS_TIMEOUT (100*1000*10)
> +
> +
> +static void smbus_delay(void)
> +{
> + outb(0x80, 0x80);
> +}
> +
> +static int smbus_wait_until_ready(unsigned smbus_io_base)
> +{
> + unsigned loops = SMBUS_TIMEOUT;
> + unsigned char byte;
> + do {
> + smbus_delay();
> + if (--loops == 0)
> + break;
> + byte = inb(smbus_io_base + SMBHSTSTAT);
> + } while(byte & 1);
> + return loops?0:-1;
> +}
> +
> +static int smbus_wait_until_done(unsigned smbus_io_base)
> +{
> + unsigned loops = SMBUS_TIMEOUT;
> + unsigned char byte;
> + do {
> + smbus_delay();
> + if (--loops == 0)
> + break;
> + byte = inb(smbus_io_base + SMBHSTSTAT);
> + } while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
> + return loops?0:-1;
> +}
> +
> +static int smbus_wait_until_blk_done(unsigned smbus_io_base)
> +{
> + unsigned loops = SMBUS_TIMEOUT;
> + unsigned char byte;
> + do {
> + smbus_delay();
> + if (--loops == 0)
> + break;
> + byte = inb(smbus_io_base + SMBHSTSTAT);
> + } while((byte&(1<<7)) == 0);
> + return loops?0:-1;
> +}
> +
> +static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
> +{
> + unsigned char global_status_register;
> + unsigned char byte;
> +
> + if (smbus_wait_until_ready(smbus_io_base) < 0) {
> + return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
> + }
> + /* setup transaction */
> + /* disable interrupts */
> + outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
> + /* set the device I'm talking too */
> + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
> + /* set the command/address... */
> + outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
> + /* set up for a byte data read */
> + outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL);
> + /* clear any lingering errors, so the transaction will run */
> + outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
> +
> + /* clear the data byte...*/
> + outb(0, smbus_io_base + SMBHSTDAT0);
> +
> + /* start the command */
> + outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL);
> +
> + /* poll for transaction completion */
> + if (smbus_wait_until_done(smbus_io_base) < 0) {
> + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
> + }
> +
> + global_status_register = inb(smbus_io_base + SMBHSTSTAT);
> +
> + /* Ignore the In Use Status... */
> + global_status_register &= ~(3 << 5);
> +
> + /* read results of transaction */
> + byte = inb(smbus_io_base + SMBHSTDAT0);
> + if (global_status_register != (1 << 1)) {
> + return SMBUS_ERROR;
> + }
> + return byte;
> +}
> +
> Index: LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_uhci.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_uhci.c
> @@ -0,0 +1,56 @@
Missing license header.
Trivial enough IMO, no research required, use your own copyright line.
> +#include <console/console.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <device/pci_ids.h>
> +#include <device/pci_ops.h>
> +#include "i3100.h"
> +
> +static void uhci_init(struct device *dev)
> +{
> + uint32_t cmd;
> +
> +#if 1
> + printk_debug("UHCI: Setting up controller.. ");
> + cmd = pci_read_config32(dev, PCI_COMMAND);
> + pci_write_config32(dev, PCI_COMMAND,
> + cmd | PCI_COMMAND_MASTER);
> +
> +
> + printk_debug("done.\n");
> +#endif
This is likely optional, try to drop it (empty function) and see
if it works (I think it usually does).
> +
> +}
> +
> +static struct pci_operations lops_pci = {
> + /* The subsystem id follows the ide controller */
Is this comment correct? Couldn't find such a note in the datasheet,
likely copy-paste and doesn't apply to this chipset?
> + .set_subsystem = 0,
> +};
> +
> +static struct device_operations uhci_ops = {
> + .read_resources = pci_dev_read_resources,
> + .set_resources = pci_dev_set_resources,
> + .enable_resources = pci_dev_enable_resources,
> + .init = uhci_init,
> + .scan_bus = 0,
> + .enable = i3100_enable,
> + .ops_pci = &lops_pci,
> +};
> +
> +static struct pci_driver uhci_driver __pci_driver = {
> + .ops = &uhci_ops,
> + .vendor = PCI_VENDOR_ID_INTEL,
> + .device = PCI_DEVICE_ID_INTEL_3100_USB,
> +};
> +
> +static struct pci_driver usb2_driver __pci_driver = {
> + .ops = &uhci_ops,
> + .vendor = PCI_VENDOR_ID_INTEL,
> + .device = PCI_DEVICE_ID_INTEL_3100_USB2,
> +};
> +static struct pci_driver usb3_driver __pci_driver = {
> + .ops = &uhci_ops,
> + .vendor = PCI_VENDOR_ID_INTEL,
> + .device = PCI_DEVICE_ID_INTEL_3100_USB3,
> +};
This one is USB 2.0 (not USB 1.1) and is already handled in *_ehci.c.
It should be dropped here, I guess. Also, *USB3 can be dropped from
pci_ids.h I think. It's already there as *_EHCI.
> +
> Index: LinuxBIOSv2-3023/src/northbridge/intel/i3100/Config.lb
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/northbridge/intel/i3100/Config.lb
> @@ -0,0 +1,10 @@
Missing license header.
> +config chip.h
> +driver northbridge.o
> +driver pciexp_porta.o
> +driver pciexp_porta1.o
> +
> +makerule raminit_test
> + depends "$(TOP)/src/northbridge/intel/i3100/raminit_test.c"
> + depends "$(TOP)/src/northbridge/intel/i3100/raminit.c"
> + action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@"
> +end
> Index: LinuxBIOSv2-3023/src/northbridge/intel/i3100/chip.h
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/northbridge/intel/i3100/chip.h
> @@ -0,0 +1,7 @@
Missing license header.
> +struct northbridge_intel_i3100_config
> +{
> + /* Interrupt line connect */
> + unsigned int intrline;
u16?
> +};
> +
> +extern struct chip_operations northbridge_intel_i3100_ops;
> Index: LinuxBIOSv2-3023/src/northbridge/intel/i3100/i3100.h
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/northbridge/intel/i3100/i3100.h
> @@ -0,0 +1,44 @@
Missing license header.
> +#define VID 0X00
> +#define DID 0X02
> +#define PCICMD 0X04
> +#define PCISTS 0X06
> +#define RID 0X08
The first few entries can be dropped, they're generic PCI stuff which is
already defined in include/device/pci_def.h.
> +#define IURBASE 0X14
> +#define MCHCFG0 0X50
> +#define MCHSCRB 0X52
> +#define FDHC 0X58
> +#define PAM 0X59
> +#define DRB 0X60
> +#define DRA 0X70
> +#define DRT 0X78
> +#define DRC 0X7C
> +#define DRM 0X80
> +#define DRORC 0X82
> +#define ECCDIAG 0X84
> +#define SDRC 0X88
> +#define CKDIS 0X8C
> +#define CKEDIS 0X8D
> +#define DDRCSR 0X9A
> +#define DEVPRES 0X9C
> +#define DEVPRES_D0F0 (1 << 0)
> +#define DEVPRES_D1F0 (1 << 1)
> +#define DEVPRES_D2F0 (1 << 2)
> +#define DEVPRES_D3F0 (1 << 3)
> +#define DEVPRES_D4F0 (1 << 4)
> +#define DEVPRES_D5F0 (1 << 5)
> +#define DEVPRES_D6F0 (1 << 6)
> +#define DEVPRES_D7F0 (1 << 7)
> +#define ESMRC 0X9D
> +#define SMRC 0X9E
> +#define EXSMRC 0X9F
> +#define DDR2ODTC 0XB0
> +#define TOLM 0XC4
> +#define REMAPBASE 0XC6
> +#define REMAPLIMIT 0XC8
> +#define REMAPOFFSET 0XCA
> +#define TOM 0XCC
> +#define EXPECBASE 0XCE
> +#define DEVPRES1 0XF4
> +#define DEVPRES1_D0F1 (1 << 5)
> +#define DEVPRES1_D8F0 (1 << 1)
> +#define MSCFG 0XF6
> Index: LinuxBIOSv2-3023/src/northbridge/intel/i3100/memory_initialized.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/northbridge/intel/i3100/memory_initialized.c
> @@ -0,0 +1,13 @@
Missing license header.
Why is this an extra file? Can it be merged somewhere sensibly?
> +#include "i3100.h"
> +#define NB_DEV PCI_DEV(0, 0, 0)
> +
> +static inline int memory_initialized(void)
> +{
> + uint32_t drc;
> + drc = pci_read_config32(NB_DEV, DRC);
> + //print_debug("memory_initialized: DRC: ");
> + //print_debug_hex32(drc);
> + //print_debug("\r\n");
> +
> + return (drc & (1<<29));
> +}
> Index: LinuxBIOSv2-3023/src/northbridge/intel/i3100/northbridge.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/northbridge/intel/i3100/northbridge.c
> @@ -0,0 +1,270 @@
Missing license header.
> +#include <console/console.h>
> +#include <arch/io.h>
> +#include <stdint.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <device/pci_ids.h>
> +#include <device/hypertransport.h>
> +#include <stdlib.h>
> +#include <string.h>
> +#include <bitops.h>
> +#include <cpu/cpu.h>
> +#include "chip.h"
> +#include "northbridge.h"
> +#include "i3100.h"
> +
> +
> +static unsigned int max_bus;
> +
> +static void ram_resource(device_t dev, unsigned long index,
> + unsigned long basek, unsigned long sizek)
> +{
> + struct resource *resource;
> +
> + resource = new_resource(dev, index);
> + resource->base = ((resource_t)basek) << 10;
> + resource->size = ((resource_t)sizek) << 10;
> + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
> + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
> +}
> +
> +
> +static void pci_domain_read_resources(device_t dev)
> +{
> + struct resource *resource;
> +
> + /* Initialize the system wide io space constraints */
> + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
> + resource->base = 0;
> + resource->size = 0;
> + resource->align = 0;
> + resource->gran = 0;
> + resource->limit = 0xffffUL;
> + resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
> +
> + /* Initialize the system wide memory resources constraints */
> + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
> + resource->base = 0;
> + resource->size = 0;
> + resource->align = 0;
> + resource->gran = 0;
> + resource->limit = 0xffffffffUL;
> + resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
> +}
> +
> +static void tolm_test(void *gp, struct device *dev, struct resource *new)
> +{
> + struct resource **best_p = gp;
> + struct resource *best;
> + best = *best_p;
> + if (!best || (best->base > new->base)) {
> + best = new;
> + }
> + *best_p = best;
> +}
> +
> +static uint32_t find_pci_tolm(struct bus *bus)
> +{
> + struct resource *min;
> + uint32_t tolm;
> + min = 0;
> + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
> + tolm = 0xffffffffUL;
> + if (min && tolm > min->base) {
> + tolm = min->base;
> + }
> + return tolm;
> +}
> +
> +
> +static void pci_domain_set_resources(device_t dev)
> +{
> + device_t mc_dev;
> + uint32_t pci_tolm;
> +
> + pci_tolm = find_pci_tolm(&dev->link[0]);
> +
> +#if 1
> + printk_debug("PCI mem marker = %x\n", pci_tolm);
> +#endif
> + /* FIXME Me temporary hack */
> + if(pci_tolm > 0xe0000000)
> + pci_tolm = 0xe0000000;
> + /* Ensure pci_tolm is 128M aligned */
> + pci_tolm &= 0xf8000000;
> + mc_dev = dev->link[0].children;
> + if (mc_dev) {
> + /* Figure out which areas are/should be occupied by RAM.
> + * This is all computed in kilobytes and converted to/from
> + * the memory controller right at the edges.
> + * Having different variables in different units is
> + * too confusing to get right. Kilobytes are good up to
> + * 4 Terabytes of RAM...
> + */
> + uint16_t tolm_r, remapbase_r, remaplimit_r, remapoffset_r;
> + unsigned long tomk, tolmk;
> + unsigned long remapbasek, remaplimitk, remapoffsetk;
> +
> + /* Get the Top of Memory address, units are 128M */
> + tomk = ((unsigned long)pci_read_config16(mc_dev, TOM)) << 17;
> + /* Compute the Top of Low Memory */
> + tolmk = (pci_tolm & 0xf8000000) >> 10;
> +
> + if (tolmk >= tomk) {
> + /* The PCI hole does not overlap memory
> + * we won't use the remap window.
> + */
> + tolmk = tomk;
> + remapbasek = 0x3ff << 16;
> + remaplimitk = 0 << 16;
> + remapoffsetk = 0 << 16;
> + }
> + else {
> + /* The PCI memory hole overlaps memory
> + * setup the remap window.
> + */
> + /* Find the bottom of the remap window
> + * is it above 4G?
> + */
> + remapbasek = 4*1024*1024;
> + if (tomk > remapbasek) {
> + remapbasek = tomk;
> + }
> + /* Find the limit of the remap window */
> + remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
> + /* Find the offset of the remap window from tolm */
> + remapoffsetk = remapbasek - tolmk;
> + }
> + /* Write the ram configruation registers,
> + * preserving the reserved bits.
> + */
> + tolm_r = pci_read_config16(mc_dev, 0xc4);
> + tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
> + pci_write_config16(mc_dev, 0xc4, tolm_r);
> +
> + remapbase_r = pci_read_config16(mc_dev, 0xc6);
> + remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
> + pci_write_config16(mc_dev, 0xc6, remapbase_r);
> +
> + remaplimit_r = pci_read_config16(mc_dev, 0xc8);
> + remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
> + pci_write_config16(mc_dev, 0xc8, remaplimit_r);
> +
> + remapoffset_r = pci_read_config16(mc_dev, 0xca);
> + remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);
> + pci_write_config16(mc_dev, 0xca, remapoffset_r);
> +
> + /* Report the memory regions */
> + ram_resource(dev, 3, 0, 640);
> + ram_resource(dev, 4, 768, (tolmk - 768));
> + if (tomk > 4*1024*1024) {
> + ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
> + }
> + if (remaplimitk >= remapbasek) {
> + ram_resource(dev, 6, remapbasek,
> + (remaplimitk + 64*1024) - remapbasek);
> + }
> + }
> + assign_resources(&dev->link[0]);
> +}
> +
> +static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
> +{
> + max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
> + if (max > max_bus) {
> + max_bus = max;
> + }
> + return max;
> +}
> +
> +static struct device_operations pci_domain_ops = {
> + .read_resources = pci_domain_read_resources,
> + .set_resources = pci_domain_set_resources,
> + .enable_resources = enable_childrens_resources,
> + .init = 0,
> + .scan_bus = pci_domain_scan_bus,
> + .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
> +};
> +
> +static void mc_read_resources(device_t dev)
> +{
> + struct resource *resource;
> +
> + pci_dev_read_resources(dev);
> +
> + resource = new_resource(dev, 0xcf);
> + resource->base = 0xe0000000;
> + resource->size = max_bus * 4096*256;
> + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
> +}
> +
> +static void mc_set_resources(device_t dev)
> +{
> + struct resource *resource, *last;
> +
> + last = &dev->resource[dev->resources];
> + resource = find_resource(dev, 0xcf);
> + if (resource) {
> + report_resource_stored(dev, resource, "<mmconfig>");
> + }
> + pci_dev_set_resources(dev);
> +}
> +
> +static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
> +{
> + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
> + ((device & 0xffff) << 16) | (vendor & 0xffff));
> +}
> +
> +static struct pci_operations intel_pci_ops = {
> + .set_subsystem = intel_set_subsystem,
> +};
> +
> +static struct device_operations mc_ops = {
> + .read_resources = mc_read_resources,
> + .set_resources = mc_set_resources,
> + .enable_resources = pci_dev_enable_resources,
> + .init = 0,
> + .scan_bus = 0,
> + .ops_pci = &intel_pci_ops,
> +};
> +
> +static struct pci_driver mc_driver __pci_driver = {
> + .ops = &mc_ops,
> + .vendor = PCI_VENDOR_ID_INTEL,
> + .device = 0x3590,
Why no #define from pci_ids.h here?
> +};
> +
> +static void cpu_bus_init(device_t dev)
> +{
> + initialize_cpus(&dev->link[0]);
> +}
> +
> +static void cpu_bus_noop(device_t dev)
> +{
> +}
> +
> +static struct device_operations cpu_bus_ops = {
> + .read_resources = cpu_bus_noop,
> + .set_resources = cpu_bus_noop,
> + .enable_resources = cpu_bus_noop,
> + .init = cpu_bus_init,
> + .scan_bus = 0,
> +};
> +
> +
> +static void enable_dev(device_t dev)
> +{
> + /* Set the operations if it is a special bus type */
> + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
> + dev->ops = &pci_domain_ops;
> + }
> + else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
> + dev->ops = &cpu_bus_ops;
> + }
> +}
> +
> +struct chip_operations northbridge_intel_i3100_ops = {
> + CHIP_NAME("Intel 3100 Northbridge")
> + .enable_dev = enable_dev,
> +};
> Index: LinuxBIOSv2-3023/src/northbridge/intel/i3100/northbridge.h
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/northbridge/intel/i3100/northbridge.h
> @@ -0,0 +1,8 @@
Missing license header.
> +#ifndef NORTHBRIDGE_INTEL_I3100_H
> +#define NORTHBRIDGE_INTEL_I3100_H
> +
> +extern unsigned int i3100_scan_root_bus(device_t root, unsigned int max);
> +
> +
> +#endif /* NORTHBRIDGE_INTEL_I3100_H */
> +
> Index: LinuxBIOSv2-3023/src/northbridge/intel/i3100/pciexp_porta.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/northbridge/intel/i3100/pciexp_porta.c
> @@ -0,0 +1,60 @@
Missing license header (sorry, I keep repeating myself ;-) But every
file needs a proper license header, otherwise we can't commit).
> +#include <console/console.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <device/pci_ids.h>
> +#include <device/pci_ops.h>
> +#include <device/pciexp.h>
> +#include <arch/io.h>
> +#include "chip.h"
> +#include <part/hard_reset.h>
> +
> +typedef struct northbridge_intel_i3100_config config_t;
> +
> +static void pcie_init(struct device *dev)
> +{
> + config_t *config;
> +
> + /* Get the chip configuration */
> + config = dev->chip_info;
> +
> + if(config->intrline) {
> + pci_write_config32(dev, 0x3c, config->intrline);
> + }
> +
> +}
> +
> +static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
> +{
> + uint16_t val;
> + uint16_t ctl;
> + int flag = 0;
> + do {
> + val = pci_read_config16(dev, 0x76);
> + printk_debug("pcie porta 0x76: %02x\n", val);
> + if((val & (1<<10) )&&(!flag)) { /* training error */
> + ctl = pci_read_config16(dev, 0x74);
> + pci_write_config16(dev, 0x74, (ctl | (1<<5)));
> + val = pci_read_config16(dev, 0x76);
> + printk_debug("pcie porta reset 0x76: %02x\n", val);
> + flag=1;
> + hard_reset();
> + }
> + } while ( val & (3<<10) );
> + return pciexp_scan_bridge(dev, max);
> +}
> +
> +static struct device_operations pcie_ops = {
> + .read_resources = pci_bus_read_resources,
> + .set_resources = pci_dev_set_resources,
> + .enable_resources = pci_bus_enable_resources,
> + .init = pcie_init,
> + .scan_bus = pcie_scan_bridge,
> + .reset_bus = pci_bus_reset,
> + .ops_pci = 0,
> +};
> +
> +static struct pci_driver pci_driver __pci_driver = {
> + .ops = &pcie_ops,
> + .vendor = PCI_VENDOR_ID_INTEL,
> + .device = PCI_DEVICE_ID_INTEL_PCIE_QA,
> +};
> Index: LinuxBIOSv2-3023/src/northbridge/intel/i3100/pciexp_porta1.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/northbridge/intel/i3100/pciexp_porta1.c
> @@ -0,0 +1,39 @@
Missing license header.
Not sure if it makes sense splitting this up. You you also merge
pciexp_porta.c and pciexp_porta1.c into one file.
> +#include <console/console.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <device/pci_ids.h>
> +#include <device/pci_ops.h>
> +#include <device/pciexp.h>
> +#include <arch/io.h>
> +#include "chip.h"
> +
> +typedef struct northbridge_intel_i3100_config config_t;
> +
> +static void pcie_init(struct device *dev)
> +{
> + config_t *config;
> +
> + /* Get the chip configuration */
> + config = dev->chip_info;
> +
> + if(config->intrline) {
> + pci_write_config32(dev, 0x3c, config->intrline);
> + }
> +
> +}
> +
> +static struct device_operations pcie_ops = {
> + .read_resources = pci_bus_read_resources,
> + .set_resources = pci_dev_set_resources,
> + .enable_resources = pci_bus_enable_resources,
> + .init = pcie_init,
> + .scan_bus = pciexp_scan_bridge,
> + .reset_bus = pci_bus_reset,
> + .ops_pci = 0,
> +};
> +
> +static struct pci_driver pci_driver __pci_driver = {
> + .ops = &pcie_ops,
> + .vendor = PCI_VENDOR_ID_INTEL,
> + .device = PCI_DEVICE_ID_INTEL_PCIE_QA1,
> +};
> Index: LinuxBIOSv2-3023/src/northbridge/intel/i3100/raminit.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/northbridge/intel/i3100/raminit.c
> @@ -0,0 +1,1218 @@
Missing license header.
Scary stuff below, way too much for me to review all at once right now,
my head is already burning ;-)
Please split up the patch into multiple ones (with the above fixes) and
repost, e.g. four patches, one for NB / SB / superio / board.
> +#include <cpu/x86/mem.h>
> +#include <cpu/x86/mtrr.h>
> +#include <cpu/x86/cache.h>
> +#include "raminit.h"
> +#include "i3100.h"
> +
> +#define BAR 0x90000000
Add a comment here. What is BAR? Maybe a more specific name.
> +
> +static void sdram_set_registers(const struct mem_controller *ctrl)
> +{
> + static const unsigned int register_values[] = {
> +
> + /* CKDIS 0x8c disable clocks */
> + PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
> +
> + /* 0x9c Device present and extended RAM control
> + * DEVPRES is very touchy, hard code the initialization
> + * of PCI-E ports here.
> + */
> + PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG,
> +
> + /* 0xc8 Remap RAM base and limit off */
> + PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000,
> +
> + /* ??? */
> + PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000,
> + PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a,
> +
> + /* 0x50 scrub */
> + PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */
> +
> + /* 0x58 0x5c PAM */
> + PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
> + PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
> +
> + /* 0xf4 */
> + PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
> +
> + /* 0x14 */
> + PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0,
> + };
> + int i;
> + int max;
> +
> + max = sizeof(register_values)/sizeof(register_values[0]);
> + for(i = 0; i < max; i += 3) {
> + device_t dev;
> + unsigned where;
> + unsigned long reg;
> + dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
> + where = register_values[i] & 0xff;
> + reg = pci_read_config32(dev, where);
> + reg &= register_values[i+1];
> + reg |= register_values[i+2];
> + pci_write_config32(dev, where, reg);
> + }
> + print_spew("done.\r\n");
> +}
> +
> +
> +
> +struct dimm_size {
> + unsigned long side1;
> + unsigned long side2;
> +};
> +
> +static struct dimm_size spd_get_dimm_size(unsigned device)
> +{
> + /* Calculate the log base 2 size of a DIMM in bits */
> + struct dimm_size sz;
> + int value, low, ddr2;
> + sz.side1 = 0;
> + sz.side2 = 0;
> +
> + /* Note it might be easier to use byte 31 here, it has the DIMM size as
> + * a multiple of 4MB. The way we do it now we can size both
> + * sides of an assymetric dimm.
> + */
> + value = spd_read_byte(device, 3); /* rows */
> + if (value < 0) goto hw_err;
> + if ((value & 0xf) == 0) goto val_err;
> + sz.side1 += value & 0xf;
> +
> + value = spd_read_byte(device, 4); /* columns */
> + if (value < 0) goto hw_err;
> + if ((value & 0xf) == 0) goto val_err;
> + sz.side1 += value & 0xf;
> +
> + value = spd_read_byte(device, 17); /* banks */
> + if (value < 0) goto hw_err;
> + if ((value & 0xff) == 0) goto val_err;
> + sz.side1 += log2(value & 0xff);
> +
> + /* Get the module data width and convert it to a power of two */
> + value = spd_read_byte(device, 7); /* (high byte) */
> + if (value < 0) goto hw_err;
> + value &= 0xff;
> + value <<= 8;
> +
> + low = spd_read_byte(device, 6); /* (low byte) */
> + if (low < 0) goto hw_err;
> + value = value | (low & 0xff);
> + if ((value != 72) && (value != 64)) goto val_err;
> + sz.side1 += log2(value);
> +
> + /* side 2 */
> + value = spd_read_byte(device, 5); /* number of physical banks */
> +
> + if (value < 0) goto hw_err;
> + value &= 7;
> + value++;
> + if (value == 1) goto out;
> + if (value != 2) goto val_err;
> +
> + /* Start with the symmetrical case */
> + sz.side2 = sz.side1;
> +
> + value = spd_read_byte(device, 3); /* rows */
> + if (value < 0) goto hw_err;
> + if ((value & 0xf0) == 0) goto out; /* If symmetrical we are done */
> + sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */
> + sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */
> +
> + value = spd_read_byte(device, 4); /* columns */
> + if (value < 0) goto hw_err;
> + if ((value & 0xff) == 0) goto val_err;
> + sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */
> + sz.side2 += ((value >> 4) & 0x0f); /* Add in columns on side 2 */
> + goto out;
> +
> + val_err:
> + die("Bad SPD value\r\n");
> + /* If an hw_error occurs report that I have no memory */
> + hw_err:
> + sz.side1 = 0;
> + sz.side2 = 0;
> + out:
> + return sz;
> +
> +}
> +
> +static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
> +{
> + int i;
> + int cum;
> +
> + for(i = cum = 0; i < DIMM_SOCKETS; i++) {
> + struct dimm_size sz;
> + if (dimm_mask & (1 << i)) {
> + sz = spd_get_dimm_size(ctrl->channel0[i]);
> + if (sz.side1 < 29) {
> + return -1; /* Report SPD error */
> + }
> + /* convert bits to multiples of 64MB */
> + sz.side1 -= 29;
> + cum += (1 << sz.side1);
> + /* DRB = 0x60 */
> + pci_write_config8(ctrl->f0, DRB + (i*2), cum);
> + if( sz.side2 > 28) {
> + sz.side2 -= 29;
> + cum += (1 << sz.side2);
> + }
> + pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
> + }
> + else {
> + pci_write_config8(ctrl->f0, DRB + (i*2), cum);
> + pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
> + }
> + }
> + cum >>= 1;
> + /* set TOM top of memory 0xcc */
> + pci_write_config16(ctrl->f0, TOM, cum);
> + /* set TOLM top of low memory */
> + if(cum > 0x18) {
> + cum = 0x18;
> + }
> + cum <<= 11;
> + /* 0xc4 TOLM */
> + pci_write_config16(ctrl->f0, TOLM, cum);
> + return 0;
> +}
> +
> +
> +static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
> +{
> + unsigned dimm_mask;
> + int i;
> + dimm_mask = 0;
> + for(i = 0; i < DIMM_SOCKETS; i++) {
> + int byte;
> + unsigned device;
> + device = ctrl->channel0[i];
> + if (device) {
> + byte = spd_read_byte(device, 2); /* Type */
> + if (byte == 8) {
> + dimm_mask |= (1 << i);
> + }
> + }
> + device = ctrl->channel1[i];
> + if (device) {
> + byte = spd_read_byte(device, 2);
> + if (byte == 8) {
> + dimm_mask |= (1 << (i + DIMM_SOCKETS));
> + }
> + }
> + }
> + return dimm_mask;
> +}
> +
> +
> +static int spd_set_row_attributes(const struct mem_controller *ctrl,
> + long dimm_mask)
> +{
> +
> + int value;
> + int reg;
> + int dra;
> + int cnt;
> +
> + dra = 0;
> + for(cnt=0; cnt < 4; cnt++) {
> + if (!(dimm_mask & (1 << cnt))) {
> + continue;
> + }
> + reg =0;
> + value = spd_read_byte(ctrl->channel0[cnt], 3); /* rows */
> + if (value < 0) goto hw_err;
> + if ((value & 0xf) == 0) goto val_err;
> + reg += value & 0xf;
> +
> + value = spd_read_byte(ctrl->channel0[cnt], 4); /* columns */
> + if (value < 0) goto hw_err;
> + if ((value & 0xf) == 0) goto val_err;
> + reg += value & 0xf;
> +
> + value = spd_read_byte(ctrl->channel0[cnt], 17); /* banks */
> + if (value < 0) goto hw_err;
> + if ((value & 0xff) == 0) goto val_err;
> + reg += log2(value & 0xff);
> +
> + /* Get the device width and convert it to a power of two */
> + value = spd_read_byte(ctrl->channel0[cnt], 13);
> + if (value < 0) goto hw_err;
> + value = log2(value & 0xff);
> + reg += value;
> + if(reg < 27) goto hw_err;
> + reg -= 27;
> + reg += (value << 2);
> +
> + dra += reg << (cnt*8);
> + value = spd_read_byte(ctrl->channel0[cnt], 5);
> + if (value & 2)
> + dra += reg << ((cnt*8)+4);
> + }
> +
> + /* 0x70 DRA */
> + pci_write_config32(ctrl->f0, DRA, dra);
> + goto out;
> +
> + val_err:
> + die("Bad SPD value\r\n");
> + /* If an hw_error occurs report that I have no memory */
> + hw_err:
> + dra = 0;
> + out:
> + return dra;
> +
> +}
> +
> +
> +static int spd_set_drt_attributes(const struct mem_controller *ctrl,
> + long dimm_mask, uint32_t drc)
> +{
> + int value;
> + int reg;
> + uint32_t drt;
> + int cnt;
> + int first_dimm;
> + int cas_latency=0;
> + int latency;
> + uint32_t index = 0;
> + uint32_t index2 = 0;
> + static const unsigned char cycle_time[3] = {0x75,0x60,0x50};
> + static const int latency_indicies[] = { 26, 23, 9 };
> +
> + /* 0x78 DRT */
> + drt = pci_read_config32(ctrl->f0, DRT);
> + drt &= 3; /* save bits 1:0 */
> +
> + for(first_dimm = 0; first_dimm < 4; first_dimm++) {
> + if (dimm_mask & (1 << first_dimm))
> + break;
> + }
> +
> + drt |= (1<<6); /* back to back write turn around */
> +
> + drt |= (3<<18); /* Trasmax */
> +
> + for(cnt=0; cnt < 4; cnt++) {
> + if (!(dimm_mask & (1 << cnt))) {
> + continue;
> + }
> + reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */
> + /* Compute the lowest cas latency supported */
> + latency = log2(reg) -2;
> +
> + /* Loop through and find a fast clock with a low latency */
> + for(index = 0; index < 3; index++, latency++) {
> + if ((latency < 2) || (latency > 4) ||
> + (!(reg & (1 << latency)))) {
> + continue;
> + }
> + value = spd_read_byte(ctrl->channel0[cnt],
> + latency_indicies[index]);
> +
> + if(value <= cycle_time[drc&3]) {
> + if( latency > cas_latency) {
> + cas_latency = latency;
> + }
> + break;
> + }
> + }
> + }
> + index = (cas_latency-2);
> + if((index)==0) cas_latency = 20;
> + else if((index)==1) cas_latency = 25;
> + else cas_latency = 30;
> +
> + for(cnt=0;cnt<4;cnt++) {
> + if (!(dimm_mask & (1 << cnt))) {
> + continue;
> + }
> + reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff;
> + if(((index>>8)&0x0ff)<reg) {
> + index &= ~(0x0ff << 8);
> + index |= (reg << 8);
> + }
> + reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;
> + if(((index>>16)&0x0ff)<reg) {
> + index &= ~(0x0ff << 16);
> + index |= (reg<<16);
> + }
> + reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;
> + if(((index2>>0)&0x0ff)<reg) {
> + index2 &= ~(0x0ff << 0);
> + index2 |= (reg<<0);
> + }
> + reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;
> + if(((index2>>8)&0x0ff)<reg) {
> + index2 &= ~(0x0ff << 8);
> + index2 |= (reg<<8);
> + }
> + reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;
> + if(((index2>>16)&0x0ff)<reg) {
> + index2 &= ~(0x0ff << 16);
> + index2 |= (reg<<16);
> + }
> + }
> +
> + /* get dimm speed */
> + value = cycle_time[drc&3];
> + if(value <= 0x50) { /* 200 MHz */
> + if((index&7) > 2) {
> + drt |= (2<<2); /* CAS latency 4 */
> + cas_latency = 40;
> + } else {
> + drt |= (1<<2); /* CAS latency 3 */
> + cas_latency = 30;
> + }
> + if((index&0x0ff00)<=0x03c00) {
> + drt |= (1<<8); /* Trp RAS Precharg */
> + } else {
> + drt |= (2<<8); /* Trp RAS Precharg */
> + }
> +
> + /* Trcd RAS to CAS delay */
> + if((index2&0x0ff)<=0x03c) {
> + drt |= (0<<10);
> + } else {
> + drt |= (1<<10);
> + }
> +
> + /* Tdal Write auto precharge recovery delay */
> + drt |= (1<<12);
> +
> + /* Trc TRS min */
> + if((index2&0x0ff00)<=0x03700)
> + drt |= (0<<14);
> + else if((index2&0xff00)<=0x03c00)
> + drt |= (1<<14);
> + else
> + drt |= (2<<14); /* spd 41 */
> +
> + drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */
> +
> + /* Trrd Row Delay */
> + if((index&0x0ff0000)<=0x0140000) {
> + drt |= (0<<20);
> + } else if((index&0x0ff0000)<=0x0280000) {
> + drt |= (1<<20);
> + } else if((index&0x0ff0000)<=0x03c0000) {
> + drt |= (2<<20);
> + } else {
> + drt |= (3<<20);
> + }
> +
> + /* Trfc Auto refresh cycle time */
> + if((index2&0x0ff0000)<=0x04b0000) {
> + drt |= (0<<22);
> + } else if((index2&0x0ff0000)<=0x0690000) {
> + drt |= (1<<22);
> + } else {
> + drt |= (2<<22);
> + }
> + /* Docs say use 55 for all 200Mhz */
> + drt |= (0x055<<24);
> + }
> + else if(value <= 0x60) { /* 167 Mhz */
> + /* according to new documentation CAS latency is 00
> + * for bits 3:2 for all 167 Mhz
> + drt |= ((index&3)<<2); */ /* set CAS latency */
> + if((index&0x0ff00)<=0x03000) {
> + drt |= (1<<8); /* Trp RAS Precharg */
> + } else {
> + drt |= (2<<8); /* Trp RAS Precharg */
> + }
> +
> + /* Trcd RAS to CAS delay */
> + if((index2&0x0ff)<=0x030) {
> + drt |= (0<<10);
> + } else {
> + drt |= (1<<10);
> + }
> +
> + /* Tdal Write auto precharge recovery delay */
> + drt |= (2<<12);
> +
> + /* Trc TRS min */
> + drt |= (2<<14); /* spd 41, but only one choice */
> +
> + drt |= (2<<16); /* Twr not defined for DDR docs say 2 */
> +
> + /* Trrd Row Delay */
> + if((index&0x0ff0000)<=0x0180000) {
> + drt |= (0<<20);
> + } else if((index&0x0ff0000)<=0x0300000) {
> + drt |= (1<<20);
> + } else {
> + drt |= (2<<20);
> + }
> +
> + /* Trfc Auto refresh cycle time */
> + if((index2&0x0ff0000)<=0x0480000) {
> + drt |= (0<<22);
> + } else if((index2&0x0ff0000)<=0x0780000) {
> + drt |= (2<<22);
> + } else {
> + drt |= (2<<22);
> + }
> + /* Docs state to use 99 for all 167 Mhz */
> + drt |= (0x099<<24);
> + }
> + else if(value <= 0x75) { /* 133 Mhz */
> + drt |= ((index&3)<<2); /* set CAS latency */
> + if((index&0x0ff00)<=0x03c00) {
> + drt |= (1<<8); /* Trp RAS Precharg */
> + } else {
> + drt |= (2<<8); /* Trp RAS Precharg */
> + }
> +
> + /* Trcd RAS to CAS delay */
> + if((index2&0x0ff)<=0x03c) {
> + drt |= (0<<10);
> + } else {
> + drt |= (1<<10);
> + }
> +
> + /* Tdal Write auto precharge recovery delay */
> + drt |= (1<<12);
> +
> + /* Trc TRS min */
> + drt |= (2<<14); /* spd 41, but only one choice */
> +
> + drt |= (1<<16); /* Twr not defined for DDR docs say 1 */
> +
> + /* Trrd Row Delay */
> + if((index&0x0ff0000)<=0x01e0000) {
> + drt |= (0<<20);
> + } else if((index&0x0ff0000)<=0x03c0000) {
> + drt |= (1<<20);
> + } else {
> + drt |= (2<<20);
> + }
> +
> + /* Trfc Auto refresh cycle time */
> + if((index2&0x0ff0000)<=0x04b0000) {
> + drt |= (0<<22);
> + } else if((index2&0x0ff0000)<=0x0780000) {
> + drt |= (2<<22);
> + } else {
> + drt |= (2<<22);
> + }
> +
> + /* Based on CAS latency */
> + if(index&7)
> + drt |= (0x099<<24);
> + else
> + drt |= (0x055<<24);
> +
> + }
> + else {
> + die("Invalid SPD 9 bus speed.\r\n");
> + }
> +
> + /* 0x78 DRT */
> + pci_write_config32(ctrl->f0, DRT, drt);
> +
> + return(cas_latency);
> +}
> +
> +static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
> + long dimm_mask)
> +{
> + int value;
> + int drc;
> + int cnt;
> + msr_t msr;
> + unsigned char ecc = 0xff;
> + unsigned char rate = 62;
> + static const unsigned char spd_rates[6] = {15,3,7,7,62,62};
> + static const unsigned char drc_rates[5] = {0,15,7,62,3};
> + static const unsigned char fsb_conversion[8] = {0,1,3,2,3,0,3,3};
> +
> + /* 0x7c DRC */
> + drc = pci_read_config32(ctrl->f0, DRC);
> + for(cnt=0; cnt < 4; cnt++) {
> + if (!(dimm_mask & (1 << cnt))) {
> + continue;
> + }
> + value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
> + if (value != 2) die("ERROR - Non ECC memory dimm\r\n");
> +
> + value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
> + value &= 0x0f; /* clip self refresh bit */
> + if (value > 5) goto hw_err;
> + if (rate > spd_rates[value])
> + rate = spd_rates[value];
> +
> + value = spd_read_byte(ctrl->channel0[cnt], 9); /* cycle time */
> + if (value > 0x75) goto hw_err;
> + }
> + if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
> + ecc = 0; /* ECC off in CMOS so disable it */
> + print_debug("ECC off\r\n");
> + }
> + else {
> + ecc = 1;
> + print_debug("ECC on\r\n");
> + }
> + drc &= ~(3 << 20); /* clear the ecc bits */
> + drc |= (ecc << 20); /* or in the calculated ecc bits */
> + for (cnt = 1; cnt < 5; cnt++)
> + if (drc_rates[cnt] == rate)
> + break;
> + if (cnt < 5) {
> + drc &= ~(7 << 8); /* clear the rate bits */
> + drc |= (cnt << 8);
> + }
> +
> + drc |= (1 << 26); /* set the overlap bit - the factory BIOS does */
> + drc |= (1 << 27); /* set DED retry enable - the factory BIOS does */
> + drc |= (1 << 7);
> + drc &= ~(1 << 5); /* enable ODT */
> + drc |= (1 << 4); /* independent clocks */
> +
> + /* set front side bus speed */
> + msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */
> + value = msr.lo & 0x07;
> + drc &= ~(3 << 2);
> + drc |= (fsb_conversion[value] << 2);
> +
> + /* set dram type to ddr2 */
> + drc &= ~(3 << 0);
> + drc |= (2 << 0);
> +
> + goto out;
> +
> + val_err:
> + die("Bad SPD value\r\n");
> + /* If an hw_error occurs report that I have no memory */
> + hw_err:
> + drc = 0;
> + out:
> + return drc;
> +}
> +
> +static void sdram_set_spd_registers(const struct mem_controller *ctrl)
> +{
> + long dimm_mask;
> +
> + /* Test if we can read the spd and if ram is ddr or ddr2 */
> + dimm_mask = spd_detect_dimms(ctrl);
> + if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
> + print_err("No memory for this cpu\r\n");
> + return;
> + }
> + return;
> +}
> +
> +static void do_delay(void)
> +{
> + int i;
> + unsigned char b;
> + for(i=0;i<16;i++)
> + b=inb(0x80);
> +}
> +
> +#define TIMEOUT_LOOPS 300000
> +
> +#define DCALCSR 0x100
> +#define DCALADDR 0x104
> +#define DCALDATA 0x108
> +
> +static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
> +{
> + unsigned char c1,c2;
> + unsigned int dimm,i;
> + unsigned int data32;
> + unsigned int t4;
> +
> + /* Set up northbridge values */
> + /* ODT enable */
> + pci_write_config32(ctrl->f0, SDRC, 0x30000000);
> + /* Figure out which slots are Empty, Single, or Double sided */
> + for(i=0,t4=0,c2=0;i<8;i+=2) {
> + c1 = pci_read_config8(ctrl->f0, DRB+i);
> + if(c1 == c2) continue;
> + c2 = pci_read_config8(ctrl->f0, DRB+1+i);
> + if(c1 == c2)
> + t4 |= (1 << (i*4));
> + else
> + t4 |= (2 << (i*4));
> + }
> + for(i=0;i<1;i++) {
> + if((t4&0x0f) == 1) {
> + if( ((t4>>8)&0x0f) == 0 ) {
> + data32 = 0x00000010; /* EEES */
> + break;
> + }
> + if ( ((t4>>16)&0x0f) == 0 ) {
> + data32 = 0x00003132; /* EESS */
> + break;
> + }
> + if ( ((t4>>24)&0x0f) == 0 ) {
> + data32 = 0x00335566; /* ESSS */
> + break;
> + }
> + data32 = 0x77bbddee; /* SSSS */
> + break;
> + }
> + if((t4&0x0f) == 2) {
> + if( ((t4>>8)&0x0f) == 0 ) {
> + data32 = 0x00003132; /* EEED */
> + break;
> + }
> + if ( ((t4>>8)&0x0f) == 2 ) {
> + data32 = 0xb373ecdc; /* EEDD */
> + break;
> + }
> + if ( ((t4>>16)&0x0f) == 0 ) {
> + data32 = 0x00b3a898; /* EESD */
> + break;
> + }
> + data32 = 0x777becdc; /* ESSD */
> + break;
> + }
> + die("Error - First dimm slot empty\r\n");
> + }
> +
> + print_debug("ODT Value = ");
> + print_debug_hex32(data32);
> + print_debug("\r\n");
> +
> + pci_write_config32(ctrl->f0, DDR2ODTC, data32);
> +
> + for(dimm=0;dimm<8;dimm+=2) {
> +
> + write32(BAR+DCALADDR, 0x0b840001);
> + write32(BAR+DCALCSR, 0x81000003 | (dimm << 20));
> +
> + for(i=0;i<1001;i++) {
> + data32 = read32(BAR+DCALCSR);
> + if(!(data32 & (1<<31)))
> + break;
> + }
> + }
> +}
> +static void set_receive_enable(const struct mem_controller *ctrl)
> +{
> + unsigned int i;
> + unsigned int cnt;
> + uint32_t recena=0;
> + uint32_t recenb=0;
> +
> + {
> + unsigned int dimm;
> + unsigned int edge;
> + int32_t data32;
> + uint32_t data32_dram;
> + uint32_t dcal_data32_0;
> + uint32_t dcal_data32_1;
> + uint32_t dcal_data32_2;
> + uint32_t dcal_data32_3;
> + uint32_t work32l;
> + uint32_t work32h;
> + uint32_t data32r;
> + int32_t recen;
> + for(dimm=0;dimm<8;dimm+=1) {
> +
> + if(!(dimm&1)) {
> + write32(BAR+DCALDATA+(17*4), 0x04020000);
> + write32(BAR+DCALCSR, 0x81800004 | (dimm << 20));
> +
> + for(i=0;i<1001;i++) {
> + data32 = read32(BAR+DCALCSR);
> + if(!(data32 & (1<<31)))
> + break;
> + }
> + if(i>=1000)
> + continue;
> +
> + dcal_data32_0 = read32(BAR+DCALDATA + 0);
> + dcal_data32_1 = read32(BAR+DCALDATA + 4);
> + dcal_data32_2 = read32(BAR+DCALDATA + 8);
> + dcal_data32_3 = read32(BAR+DCALDATA + 12);
> + }
> + else {
> + dcal_data32_0 = read32(BAR+DCALDATA + 16);
> + dcal_data32_1 = read32(BAR+DCALDATA + 20);
> + dcal_data32_2 = read32(BAR+DCALDATA + 24);
> + dcal_data32_3 = read32(BAR+DCALDATA + 28);
> + }
> +
> + /* check if bank is installed */
> + if((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
> + continue;
> + /* Calculate the timing value */
> + {
> + unsigned int bit;
> + for(i=0,edge=0,bit=63,cnt=31,data32r=0,
> + work32l=dcal_data32_1,work32h=dcal_data32_3;
> + (i<4) && bit; i++) {
> + for(;;bit--,cnt--) {
> + if(work32l & (1<<cnt))
> + break;
> + if(!cnt) {
> + work32l = dcal_data32_0;
> + work32h = dcal_data32_2;
> + cnt = 32;
> + }
> + if(!bit) break;
> + }
> + for(;;bit--,cnt--) {
> + if(!(work32l & (1<<cnt)))
> + break;
> + if(!cnt) {
> + work32l = dcal_data32_0;
> + work32h = dcal_data32_2;
> + cnt = 32;
> + }
> + if(!bit) break;
> + }
> + if(!bit) {
> + break;
> + }
> + data32 = ((bit%8) << 1);
> + if(work32h & (1<<cnt))
> + data32 += 1;
> + if(data32 < 4) {
> + if(!edge) {
> + edge = 1;
> + }
> + else {
> + if(edge != 1) {
> + data32 = 0x0f;
> + }
> + }
> + }
> + if(data32 > 12) {
> + if(!edge) {
> + edge = 2;
> + }
> + else {
> + if(edge != 2) {
> + data32 = 0x00;
> + }
> + }
> + }
> + data32r += data32;
> + }
> + }
> + work32l = dcal_data32_0;
> + work32h = dcal_data32_2;
> + recen = data32r;
> + recen += 3;
> + recen = recen>>2;
> + for(cnt=5;cnt<24;) {
> + for(;;cnt++)
> + if(!(work32l & (1<<cnt)))
> + break;
> + for(;;cnt++) {
> + if(work32l & (1<<cnt))
> + break;
> + }
> + data32 = (((cnt-1)%8)<<1);
> + if(work32h & (1<<(cnt-1))) {
> + data32++;
> + }
> + /* test for frame edge cross overs */
> + if((edge == 1) && (data32 > 12) &&
> + (((recen+16)-data32) < 3)) {
> + data32 = 0;
> + cnt += 2;
> + }
> + if((edge == 2) && (data32 < 4) &&
> + ((recen - data32) > 12)) {
> + data32 = 0x0f;
> + cnt -= 2;
> + }
> + if(((recen+3) >= data32) && ((recen-3) <= data32))
> + break;
> + }
> + cnt--;
> + cnt /= 8;
> + cnt--;
> + if(recen&1)
> + recen+=2;
> + recen >>= 1;
> + recen += (cnt*8);
> + recen+=2; /* this is not in the spec, but matches
> + the factory output, and has less failure */
> + recen <<= (dimm/2) * 8;
> + if(!(dimm&1)) {
> + recena |= recen;
> + }
> + else {
> + recenb |= recen;
> + }
> + }
> + }
> + /* Check for Eratta problem */
> + for(i=cnt=0;i<32;i+=8) {
> + if (((recena>>i)&0x0f)>7) {
> + cnt+= 0x101;
> + }
> + else {
> + if((recena>>i)&0x0f) {
> + cnt++;
> + }
> + }
> + }
> + if(cnt&0x0f00) {
> + cnt = (cnt&0x0f) - (cnt>>16);
> + if(cnt>1) {
> + for(i=0;i<32;i+=8) {
> + if(((recena>>i)&0x0f)>7) {
> + recena &= ~(0x0f<<i);
> + recena |= (7<<i);
> + }
> + }
> + }
> + else {
> + for(i=0;i<32;i+=8) {
> + if(((recena>>i)&0x0f)<8) {
> + recena &= ~(0x0f<<i);
> + recena |= (8<<i);
> + }
> + }
> + }
> + }
> + for(i=cnt=0;i<32;i+=8) {
> + if (((recenb>>i)&0x0f)>7) {
> + cnt+= 0x101;
> + }
> + else {
> + if((recenb>>i)&0x0f) {
> + cnt++;
> + }
> + }
> + }
> + if(cnt & 0x0f00) {
> + cnt = (cnt&0x0f) - (cnt>>16);
> + if(cnt>1) {
> + for(i=0;i<32;i+=8) {
> + if(((recenb>>i)&0x0f)>7) {
> + recenb &= ~(0x0f<<i);
> + recenb |= (7<<i);
> + }
> + }
> + }
> + else {
> + for(i=0;i<32;i+=8) {
> + if(((recenb>>8)&0x0f)<8) {
> + recenb &= ~(0x0f<<i);
> + recenb |= (8<<i);
> + }
> + }
> + }
> + }
> +
> + print_debug("Receive enable A = ");
> + print_debug_hex32(recena);
> + print_debug(", Receive enable B = ");
> + print_debug_hex32(recenb);
> + print_debug("\r\n");
> +
> + /* clear out the calibration area */
> + write32(BAR+DCALDATA+(16*4), 0x00000000);
> + write32(BAR+DCALDATA+(17*4), 0x00000000);
> + write32(BAR+DCALDATA+(18*4), 0x00000000);
> + write32(BAR+DCALDATA+(19*4), 0x00000000);
> +
> + /* No command */
> + write32(BAR+DCALCSR, 0x0000000f);
> +
> + write32(BAR+0x150, recena);
> + write32(BAR+0x154, recenb);
> +}
> +
> +
> +static void sdram_enable(int controllers, const struct mem_controller *ctrl)
> +{
> + int i;
> + int cs;
> + int cnt;
> + int cas_latency;
> + long mask;
> + uint32_t drc;
> + uint32_t data32;
> + uint32_t mode_reg;
> + uint32_t *iptr;
> + volatile unsigned long *iptrv;
> + msr_t msr;
> + uint32_t scratch;
> + uint8_t byte;
> + uint16_t data16;
> + static const struct {
> + uint32_t clkgr[4];
> + } gearing [] = {
> + /* FSB 100 */
> + {{ 0x00000010, 0x00000000, 0x00000002, 0x00000001}},
> + /* FSB 133 */
> + {{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
> + /* FSB 167 */
> + {{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
> + /* N/A */
> + {{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}},
> + };
> +
> + static const uint32_t dqs_data[] = {
> + 0xffffffff, 0xffffffff, 0x000000ff,
> + 0xffffffff, 0xffffffff, 0x000000ff,
> + 0xffffffff, 0xffffffff, 0x000000ff,
> + 0xffffffff, 0xffffffff, 0x000000ff,
> + 0xffffffff, 0xffffffff, 0x000000ff,
> + 0xffffffff, 0xffffffff, 0x000000ff,
> + 0xffffffff, 0xffffffff, 0x000000ff,
> + 0xffffffff, 0xffffffff, 0x000000ff};
> +
> + mask = spd_detect_dimms(ctrl);
> + print_debug("Starting SDRAM Enable\r\n");
> +
> + /* 0x80 */
> +#ifdef DIMM_MAP_LOGICAL
> + pci_write_config32(ctrl->f0, DRM,
> + 0x00410000 | DIMM_MAP_LOGICAL);
> +#else
> + pci_write_config32(ctrl->f0, DRM, 0x00411248);
> +#endif
> + /* set dram type and Front Side Bus freq. */
> + drc = spd_set_dram_controller_mode(ctrl, mask);
> + if( drc == 0) {
> + die("Error calculating DRC\r\n");
> + }
> + data32 = drc & ~(3 << 20); /* clear ECC mode */
> + data32 = data32 & ~(7 << 8); /* clear refresh rates */
> + data32 = data32 | (1 << 5); /* temp turn off ODT */
> + /* Set gearing, then dram controller mode */
> + /* drc bits 3:2 = FSB speed */
> + for(iptr = gearing[(drc>>2)&3].clkgr,cnt=0;cnt<4;cnt++) {
> + pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
> + }
> + /* 0x7c DRC */
> + pci_write_config32(ctrl->f0, DRC, data32);
> +
> + /* turn the clocks on */
> + /* 0x8c CKDIS */
> + pci_write_config16(ctrl->f0, CKDIS, 0x0000);
> +
> + /* 0x9a DDRCSR Take subsystem out of idle */
> + data16 = pci_read_config16(ctrl->f0, DDRCSR);
> + data16 &= ~(7 << 12);
> + data16 |= (1 << 12);
> + pci_write_config16(ctrl->f0, DDRCSR, data16);
> +
> + /* program row size DRB */
> + spd_set_ram_size(ctrl, mask);
> +
> + /* program page size DRA */
> + spd_set_row_attributes(ctrl, mask);
> +
> + /* program DRT timing values */
> + cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
> +
> + for(i=0;i<8;i+=2) { /* loop through each dimm to test */
> + print_debug("DIMM ");
> + print_debug_hex8(i);
> + print_debug("\r\n");
> + /* Apply NOP */
> + do_delay();
> +
> + write32(BAR+DCALCSR, (0x01000000 | (i<<20)));
> + write32(BAR+DCALCSR, (0x81000000 | (i<<20)));
> +
> + data32 = read32(BAR+DCALCSR);
> + while(data32 & 0x80000000)
> + data32 = read32(BAR+DCALCSR);
> + }
> +
> + /* Apply NOP */
> + do_delay();
> +
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR + DCALCSR, (0x81000000 | (cs<<20)));
> + data32 = read32(BAR+DCALCSR);
> + while(data32 & 0x80000000)
> + data32 = read32(BAR+DCALCSR);
> + }
> +
> + /* Precharg all banks */
> + do_delay();
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR+DCALADDR, 0x04000000);
> + write32(BAR+DCALCSR, (0x81000002 | (cs<<20)));
> + data32 = read32(BAR+DCALCSR);
> + while(data32 & 0x80000000)
> + data32 = read32(BAR+DCALCSR);
> + }
> +
> + /* EMRS dll's enabled */
> + do_delay();
> + for(cs=0;cs<8;cs+=2) {
> + /* fixme hard code AL additive latency */
> + write32(BAR+DCALADDR, 0x0b940001);
> + write32(BAR+DCALCSR, (0x81000003 | (cs<<20)));
> + data32 = read32(BAR+DCALCSR);
> + while(data32 & 0x80000000)
> + data32 = read32(BAR+DCALCSR);
> + }
> + /* MRS reset dll's */
> + do_delay();
> + if(cas_latency == 30)
> + mode_reg = 0x053a0000;
> + else
> + mode_reg = 0x054a0000;
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR+DCALADDR, mode_reg);
> + write32(BAR+DCALCSR, (0x81000003 | (cs<<20)));
> + data32 = read32(BAR+DCALCSR);
> + while(data32 & 0x80000000)
> + data32 = read32(BAR+DCALCSR);
> + }
> +
> + /* Precharg all banks */
> + do_delay();
> + do_delay();
> + do_delay();
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR+DCALADDR, 0x04000000);
> + write32(BAR+DCALCSR, (0x81000002 | (cs<<20)));
> + data32 = read32(BAR+DCALCSR);
> + while(data32 & 0x80000000)
> + data32 = read32(BAR+DCALCSR);
> + }
> +
> + /* Do 2 refreshes */
> + do_delay();
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR+DCALCSR, (0x81000001 | (cs<<20)));
> + data32 = read32(BAR+DCALCSR);
> + while(data32 & 0x80000000)
> + data32 = read32(BAR+DCALCSR);
> + }
> + do_delay();
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR+DCALCSR, (0x81000001 | (cs<<20)));
> + data32 = read32(BAR+DCALCSR);
> + while(data32 & 0x80000000)
> + data32 = read32(BAR+DCALCSR);
> + }
> + do_delay();
> + /* for good luck do 6 more */
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR+DCALCSR, (0x81000001 | (cs<<20)));
> + }
> + do_delay();
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR+DCALCSR, (0x81000001 | (cs<<20)));
> + }
> + do_delay();
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR+DCALCSR, (0x81000001 | (cs<<20)));
> + }
> + do_delay();
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR+DCALCSR, (0x81000001 | (cs<<20)));
> + }
> + do_delay();
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR+DCALCSR, (0x81000001 | (cs<<20)));
> + }
> + do_delay();
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR+DCALCSR, (0x81000001 | (cs<<20)));
> + }
> + do_delay();
> + /* MRS reset dll's normal */
> + do_delay();
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
> + write32(BAR+DCALCSR, (0x81000003 | (cs<<20)));
> + data32 = read32(BAR+DCALCSR);
> + while(data32 & 0x80000000)
> + data32 = read32(BAR+DCALCSR);
> + }
> +
> + /* Do only if DDR2 EMRS dll's enabled */
> + do_delay();
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR+DCALADDR, (0x0b940001));
> + write32(BAR+DCALCSR, (0x81000003 | (cs<<20)));
> + data32 = read32(BAR+DCALCSR);
> + while(data32 & 0x80000000)
> + data32 = read32(BAR+DCALCSR);
> + }
> +
> + do_delay();
> + /* No command */
> + write32(BAR+DCALCSR, 0x0000000f);
> +
> + /* DDR1 This is test code to copy some codes in the factory setup */
> +
> + write32(BAR, 0x00100000);
> +
> + /* enable on dimm termination */
> + set_on_dimm_termination_enable(ctrl);
> +
> + /* receive enable calibration */
> + set_receive_enable(ctrl);
> +
> + /* DQS */
> + pci_write_config32(ctrl->f0, 0x94, 0x3904aa00);
> + for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) {
> + write32(cnt, dqs_data[i]);
> + }
> + pci_write_config32(ctrl->f0, 0x94, 0x3900aa00);
> +
> + /* Enable refresh */
> + /* 0x7c DRC */
> + data32 = drc & ~(3 << 20); /* clear ECC mode */
> + pci_write_config32(ctrl->f0, DRC, data32);
> + write32(BAR+DCALCSR, 0x0008000f);
> +
> + /* clear memory and init ECC */
> + print_debug("Clearing memory\r\n");
> + for(i=0;i<64;i+=4) {
> + write32(BAR+DCALDATA+i, 0x00000000);
> + }
> +
> + for(cs=0;cs<8;cs+=2) {
> + write32(BAR+DCALCSR, (0x810831d8 | (cs<<20)));
> + data32 = read32(BAR+DCALCSR);
> + while(data32 & 0x80000000)
> + data32 = read32(BAR+DCALCSR);
> + }
> +
> + /* Bring memory subsystem on line */
> + data32 = pci_read_config32(ctrl->f0, 0x98);
> + data32 |= (1 << 31);
> + pci_write_config32(ctrl->f0, 0x98, data32);
> + /* wait for completion */
> + print_debug("Waiting for mem complete\r\n");
> + while(1) {
> + data32 = pci_read_config32(ctrl->f0, 0x98);
> + if( (data32 & (1<<31)) == 0)
> + break;
> + }
> + print_debug("Done\r\n");
> +
> + /* Set initialization complete */
> + /* 0x7c DRC */
> + drc |= (1 << 29);
> + data32 = drc & ~(3 << 20); /* clear ECC mode */
> + pci_write_config32(ctrl->f0, DRC, data32);
> +
> + /* Set the ecc mode */
> + pci_write_config32(ctrl->f0, DRC, drc);
> +
> + /* Enable memory scrubbing */
> + /* 0x52 MCHSCRB */
> + data16 = pci_read_config16(ctrl->f0, MCHSCRB);
> + data16 &= ~0x0f;
> + data16 |= ((2 << 2) | (2 << 0));
> + pci_write_config16(ctrl->f0, MCHSCRB, data16);
> +
> + /* The memory is now setup, use it */
> + cache_lbmem(MTRR_TYPE_WRBACK);
> +}
> Index: LinuxBIOSv2-3023/src/northbridge/intel/i3100/raminit.h
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/northbridge/intel/i3100/raminit.h
> @@ -0,0 +1,12 @@
Missing license header.
> +#ifndef RAMINIT_H
> +#define RAMINIT_H
> +
> +#define DIMM_SOCKETS 4
> +struct mem_controller {
> + unsigned node_id;
> + device_t f0, f1, f2, f3;
> + uint16_t channel0[DIMM_SOCKETS];
> + uint16_t channel1[DIMM_SOCKETS];
> +};
> +
> +#endif /* RAMINIT_H */
> Index: LinuxBIOSv2-3023/src/northbridge/intel/i3100/raminit_test.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/northbridge/intel/i3100/raminit_test.c
> @@ -0,0 +1,442 @@
Missing license header.
Why is this stuff needed? Does it do more than memtest86 can do?
> +#include <unistd.h>
> +#include <limits.h>
> +#include <stdint.h>
> +#include <string.h>
> +#include <setjmp.h>
> +#include <device/pci_def.h>
> +#include "i3100.h"
> +
> +jmp_buf end_buf;
> +
> +static int is_cpu_pre_c0(void)
> +{
> + return 0;
> +}
> +
> +#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
> + (((BUS) & 0xFF) << 16) | \
> + (((DEV) & 0x1f) << 11) | \
> + (((FN) & 0x07) << 8) | \
> + ((WHERE) & 0xFF))
> +
> +#define PCI_DEV(BUS, DEV, FN) ( \
> + (((BUS) & 0xFF) << 16) | \
> + (((DEV) & 0x1f) << 11) | \
> + (((FN) & 0x7) << 8))
> +
> +#define PCI_ID(VENDOR_ID, DEVICE_ID) \
> + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
> +
> +typedef unsigned device_t;
> +
> +unsigned char pci_register[256*5*3*256];
> +
> +static uint8_t pci_read_config8(device_t dev, unsigned where)
> +{
> + unsigned addr;
> + addr = dev | where;
> + return pci_register[addr];
> +}
> +
> +static uint16_t pci_read_config16(device_t dev, unsigned where)
> +{
> + unsigned addr;
> + addr = dev | where;
> + return pci_register[addr] | (pci_register[addr + 1] << 8);
> +}
Generic PCI stuff, don't we already have the same functions elsewhere?
> +
> +static uint32_t pci_read_config32(device_t dev, unsigned where)
> +{
> + unsigned addr;
> + uint32_t value;
> + addr = dev | where;
> + value = pci_register[addr] |
> + (pci_register[addr + 1] << 8) |
> + (pci_register[addr + 2] << 16) |
> + (pci_register[addr + 3] << 24);
> +
> +#if 0
> + print_debug("pcir32(");
> + print_debug_hex32(addr);
> + print_debug("):");
> + print_debug_hex32(value);
> + print_debug("\n");
> +#endif
> + return value;
> +
> +}
> +
> +static void pci_write_config8(device_t dev, unsigned where, uint8_t value)
> +{
> + unsigned addr;
> + addr = dev | where;
> + pci_register[addr] = value;
> +}
> +
> +static void pci_write_config16(device_t dev, unsigned where, uint16_t value)
> +{
> + unsigned addr;
> + addr = dev | where;
> + pci_register[addr] = value & 0xff;
> + pci_register[addr + 1] = (value >> 8) & 0xff;
> +}
> +
> +static void pci_write_config32(device_t dev, unsigned where, uint32_t value)
> +{
> + unsigned addr;
> + addr = dev | where;
> + pci_register[addr] = value & 0xff;
> + pci_register[addr + 1] = (value >> 8) & 0xff;
> + pci_register[addr + 2] = (value >> 16) & 0xff;
> + pci_register[addr + 3] = (value >> 24) & 0xff;
> +
> +#if 0
> + print_debug("pciw32(");
> + print_debug_hex32(addr);
> + print_debug(", ");
> + print_debug_hex32(value);
> + print_debug(")\n");
> +#endif
> +}
> +
> +#define PCI_DEV_INVALID (0xffffffffU)
> +static device_t pci_locate_device(unsigned pci_id, device_t dev)
> +{
> + for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
> + unsigned int id;
> + id = pci_read_config32(dev, 0);
> + if (id == pci_id) {
> + return dev;
> + }
> + }
> + return PCI_DEV_INVALID;
> +}
> +
> +
> +
> +
> +static void uart_tx_byte(unsigned char data)
> +{
> + write(STDOUT_FILENO, &data, 1);
> +}
> +static void hlt(void)
> +{
> + longjmp(end_buf, 2);
> +}
> +#include "../../../arch/i386/lib/console.c"
> +
> +unsigned long log2(unsigned long x)
> +{
> + // assume 8 bits per byte.
> + unsigned long i = 1 << (sizeof(x)*8 - 1);
> + unsigned long pow = sizeof(x) * 8 - 1;
> +
> + if (! x) {
> + static const char errmsg[] = " called with invalid parameter of 0\n";
> + write(STDERR_FILENO, __func__, sizeof(__func__) - 1);
> + write(STDERR_FILENO, errmsg, sizeof(errmsg) - 1);
> + hlt();
> + }
> + for(; i > x; i >>= 1, pow--)
> + ;
> +
> + return pow;
> +}
Ditto, this should be elsewhere, probably already is.
> +
> +typedef struct msr_struct
> +{
> + unsigned lo;
> + unsigned hi;
> +} msr_t;
msr_t is also defined elsewhere already, I think (in v3 at least).
> +
> +static inline msr_t rdmsr(unsigned index)
> +{
> + msr_t result;
> + result.lo = 0;
> + result.hi = 0;
> + return result;
> +}
> +
> +static inline void wrmsr(unsigned index, msr_t msr)
> +{
> +}
> +
> +#include "raminit.h"
> +
> +#define SIO_BASE 0x2e
Not generic, this should be configurable. Also, you used 0x4e anyway
for this board.
> +
> +static void hard_reset(void)
> +{
> + /* FIXME implement the hard reset case... */
> + longjmp(end_buf, 3);
> +}
> +
> +static void memreset_setup(void)
> +{
> + /* Nothing to do */
> +}
> +
> +static void memreset(int controllers, const struct mem_controller *ctrl)
> +{
> + /* Nothing to do */
> +}
> +
> +static inline void activate_spd_rom(const struct mem_controller *ctrl)
> +{
> + /* nothing to do */
> +}
> +
> +
> +static uint8_t spd_mt4lsdt464a[256] =
> +{
> + 0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70,
> + 0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01,
> + 0x01, 0x00, 0x0E, 0x75, 0x54, 0x00, 0x00, 0x0F, 0x0E, 0x0F,
> +
> + 0x25, 0x08, 0x15, 0x08, 0x15, 0x08, 0x00, 0x12, 0x01, 0x4E,
> + 0x9C, 0xE4, 0xB7, 0x46, 0x2C, 0xFF, 0x01, 0x02, 0x03, 0x04,
> + 0x05, 0x06, 0x07, 0x08, 0x09, 0x01, 0x02, 0x03, 0x04, 0x05,
> + 0x06, 0x07, 0x08, 0x09, 0x00,
> +};
> +
> +static uint8_t spd_micron_512MB_DDR333[256] =
> +{
> + 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60,
> + 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
> + 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
> + 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31,
> + 0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43,
> + 0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
> +};
> +
> +static uint8_t spd_micron_256MB_DDR333[256] =
> +{
> + 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60,
> + 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
> + 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
> + 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x3c, 0x48, 0x30, 0x23, 0x50, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x58, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36,
> + 0x34, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, 0x31,
> + 0x20, 0x01, 0x00, 0x03, 0x19, 0x17, 0x05, 0xb2, 0xf4, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +};
> +
> +#define MAX_DIMMS 16
> +static uint8_t spd_data[MAX_DIMMS*256];
> +
> +static unsigned spd_count, spd_fail_count;
> +static int spd_read_byte(unsigned device, unsigned address)
> +{
> + int result;
> + spd_count++;
> + if ((device < 0x50) || (device >= (0x50 +MAX_DIMMS))) {
> + result = -1;
> + }
> + else {
> + device -= 0x50;
> +
> + if (address > 256) {
> + result = -1;
> + }
> + else if (spd_data[(device << 8) | 2] != 7) {
> + result = -1;
> + }
> + else {
> + result = spd_data[(device << 8) | address];
> + }
> + }
> +#if 0
> + print_debug("spd_read_byte(");
> + print_debug_hex32(device);
> + print_debug(", ");
> + print_debug_hex32(address);
> + print_debug(") -> ");
> + print_debug_hex32(result);
> + print_debug("\n");
> +#endif
> + if (spd_count >= spd_fail_count) {
> + result = -1;
> + }
> + return result;
> +}
> +
> +/* no specific code here. this should go away completely */
> +static void coherent_ht_mainboard(unsigned cpus)
> +{
> +}
> +
> +#include "raminit.c"
> +#include "../../../sdram/generic_sdram.c"
> +
> +#define FIRST_CPU 1
> +#define SECOND_CPU 1
> +#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
> +static void raminit_main(void)
> +{
> + /*
> + * GPIO28 of 8111 will control H0_MEMRESET_L
> + * GPIO29 of 8111 will control H1_MEMRESET_L
> + */
> + static const struct mem_controller cpu[] = {
> +#if FIRST_CPU
> + {
> + .node_id = 0,
> + .f0 = PCI_DEV(0, 0x18, 0),
> + .f1 = PCI_DEV(0, 0x18, 1),
> + .f2 = PCI_DEV(0, 0x18, 2),
> + .f3 = PCI_DEV(0, 0x18, 3),
> + .channel0 = { 0x50+0, 0x50+2, 0x50+4, 0x50+6 },
> + .channel1 = { 0x50+1, 0x50+3, 0x50+5, 0x50+7 },
> + },
> +#endif
> +#if SECOND_CPU
> + {
> + .node_id = 1,
> + .f0 = PCI_DEV(0, 0x19, 0),
> + .f1 = PCI_DEV(0, 0x19, 1),
> + .f2 = PCI_DEV(0, 0x19, 2),
> + .f3 = PCI_DEV(0, 0x19, 3),
> + .channel0 = { 0x50+8, 0x50+10, 0x50+12, 0x50+14 },
> + .channel1 = { 0x50+9, 0x50+11, 0x50+13, 0x50+15 },
> + },
> +#endif
> + };
> + console_init();
> + memreset_setup();
> + sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
> +
> +}
> +
> +static void reset_tests(void)
> +{
> + /* Clear the results of any previous tests */
> + memset(pci_register, 0, sizeof(pci_register));
> + memset(spd_data, 0, sizeof(spd_data));
> + spd_count = 0;
> + spd_fail_count = UINT_MAX;
> +
> + pci_write_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP,
> + NBCAP_128Bit |
> + NBCAP_MP| NBCAP_BIG_MP |
> + /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */
> + (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) |
> + NBCAP_MEMCTRL);
> +
> + pci_write_config32(PCI_DEV(0, 0x19, 3), NORTHBRIDGE_CAP,
> + NBCAP_128Bit |
> + NBCAP_MP| NBCAP_BIG_MP |
> + /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */
> + (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) |
> + NBCAP_MEMCTRL);
> +
> +#if 0
> + pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP);
> +#endif
> +}
> +
> +static void test1(void)
> +{
> + reset_tests();
> +
> + memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
> + memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
> +#if 0
> + memcpy(&spd_data[2*256], spd_micron_512MB_DDR333, 256);
> + memcpy(&spd_data[3*256], spd_micron_512MB_DDR333, 256);
> +
> + memcpy(&spd_data[8*256], spd_micron_512MB_DDR333, 256);
> + memcpy(&spd_data[9*256], spd_micron_512MB_DDR333, 256);
> + memcpy(&spd_data[10*256], spd_micron_512MB_DDR333, 256);
> + memcpy(&spd_data[11*256], spd_micron_512MB_DDR333, 256);
> +#endif
> +
> + raminit_main();
> +
> +#if 0
> + print_debug("spd_count: ");
> + print_debug_hex32(spd_count);
> + print_debug("\r\n");
> +#endif
> +
> +}
> +
> +
> +static void do_test2(int i)
> +{
> + jmp_buf tmp_buf;
> + memcpy(&tmp_buf, &end_buf, sizeof(end_buf));
> + if (setjmp(end_buf) != 0) {
> + goto done;
> + }
> + reset_tests();
> + spd_fail_count = i;
> +
> + print_debug("\r\nSPD will fail after: ");
> + print_debug_hex32(spd_fail_count);
> + print_debug(" accesses.\r\n");
> +
> + memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
> + memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
> +
> + raminit_main();
> +
> + done:
> + memcpy(&end_buf, &tmp_buf, sizeof(end_buf));
> +}
> +
> +static void test2(void)
> +{
> + int i;
> + for(i = 0; i < 0x48; i++) {
> + do_test2(i);
> + }
> +
> +}
> +
> +int main(int argc, char **argv)
> +{
> + if (setjmp(end_buf) != 0) {
> + return -1;
> + }
> + test1();
> + test2();
> + return 0;
> +}
> Index: LinuxBIOSv2-3023/targets/intel/mtarvon/Config.lb
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/targets/intel/mtarvon/Config.lb
> @@ -0,0 +1,21 @@
Missing license header.
> +target mtarvon
> +mainboard intel/mtarvon
> +
> +## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use
coreboot
> +## (normal AND fallback images and payloads).
> +option ROM_SIZE = 2048*1024
option ROM_SIZE = 2 * 1024 * 1024
is more obvious IMO.
> +
> +## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
> +## not including any payload.
> +option ROM_IMAGE_SIZE = 0x20000
128 * 1024
> +
> +## FALLBACK_SIZE is the amount of the ROM the complete fallback image
> +## (including payload) will use
> +option FALLBACK_SIZE = ROM_SIZE
> +
> +romimage "fallback"
> + option USE_FALLBACK_IMAGE=1
> + payload ../../Aboot.elf
I'm curious, what's Aboot?
> +end
> +
> +buildrom ./linuxbios.rom ROM_SIZE "fallback"
coreboot.rom
> Index: LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_early_lpc.c
> ===================================================================
> --- /dev/null
> +++ LinuxBIOSv2-3023/src/southbridge/intel/i3100/i3100_early_lpc.c
> @@ -0,0 +1,12 @@
Missing license header.
> +static void i3100_enable_superio(void)
> +{
> + device_t dev;
> + dev = pci_locate_device(PCI_ID(0x8086, 0x2670), 0);
Use IDs from pci_ids.h, please.
> + if (dev == PCI_DEV_INVALID) {
> + outb(0xd0, 0x80);
Why the outb()? Use post_code() if it's needed.
> + die("ISA bridge not found\r\n");
> + }
> +
> + /* Enable decoding of I/O locations for SuperIO devices */
> + pci_write_config16(dev, 0x82, 0x340f);
> +}
Sorry for the long post, but there was lots of code to review :)
Again, please fix most of the issues and then repost as four smaller
patches for easier review and committing.
Thanks, Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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