[coreboot] (GSoC__SCSI boot)GSOC Midterm survey and new problem(Vendor ID mismatch)

[Zhang Rui]

Hello, Stefan

2008/7/10, Zhang Rui <zrfail at gmail.com>:
> Hello, Stefan
>
> First, the GSOC mid term evaluation comes. Please submit the mentor
> midterm survey for this "SCSI booting in coreboot" project. The
> timeline is July 7th to July 14th at 19:00 UTC.  Refer to "Survey
> Information for Mentors with Students Assigned to Them" on
> http://groups.google.com/group/google-summer-of-code-announce/web/midterm-survey-information
> Thanks.
>
>
> Second, my process and problems:
>
> 2008/7/6 Zhang Rui <zrfail at gmail.com>:
> > Hello Stefan,
> >
> > 2008/6/25, Zhang Rui <zrfail at gmail.com>:
> [...]
> > I finally find that in arch/x86/, function pci_dev_init() called
> > run_bios() in util/x86emu.
> > The order is :
> > pci_dev_init
> >      -->pci_rom_probe
> >      -->run_bios(vm86.c/biosemu.c)
> >
> > my problem is:
> > in pci_rom_probe, most rom_address is 0 and return NULL;
> > only one rom_address is 0x c0000 but the rom_header->signature is 0 so
> > it also return NULL.
> >
> > So no run_bios is running.
> >
> > How can I get run_bios() running and test my code in it?
> >
> > Best regards.
> >
> > Zhang Rui
> >
> >
> > Here is the output of qemu:
> >[...]
>
> Now I find that there is something wrong with my vgabios-cirrus.  I
> download it from www.coreboot.org by a browser and unzip it to
> "vgabios-cirrus". But actually it is only 14k. I added ".zip" to the
> file "vgabios-cirrus" and unzip it to "vgabios-cirrus.bin". And it
> works now.
>
> But new problem comes up: "Device or Vendor ID mismatch Vendor 0846,
> Device ec89"
> So run_bios() is not executed.
>
> Here is related source code:
> in device/pci_device.c, in function pci_dev_init()
>        rom = pci_rom_probe(dev);
>        if (rom == NULL)
>                return;
>        ram = pci_rom_load(dev, rom);
>        if (ram == NULL)
>                return;
>        run_bios(dev, (unsigned long)ram);
>
> run_bios is called here. But before it is called, there are two
> "return" statement. And:
>
> in device/pci_rom.c, line 111~116, in function pci_rom_probe()
>        if (dev->id.u.pci.vendor != rom_data->vendor || dev->id.u.pci.device
> != rom_data->device) {
>                printk(BIOS_ERR,
>                       "Device or Vendor ID mismatch Vendor %04x, Device %04x\n",
>                       rom_data->vendor, rom_data->device);
>                return NULL;
>        }
>
> it returns NULL here.
>
> Maybe I should clear the code in pci_dev_init() and call modified
> run_bios() (or another function run_seabios() written by myself)
> directly? And then I could test my codes in the run_bios().
>

I wrote run_seabios() in vm86.c to copy Legacybios to 0xf0000

modify pci_dev_init() in device/pci_device.c to call run_seabios() in vm86.c

Then, at line 224 in arch/x86/stage1.c, before "die("FATAL: No usable
payload found.\n");"
1. call run_address(0x000f7ad7); //0x000f7ad7 is the address of post()
in LegacyBIOS
qemu dies and can not close the qemu window.

2. call run_address(0x000f66e0); //0x000f66e0 is the entry address of
LegacyBIOS payload. And I find that 0x000f66e0 is the address of
post32() defined in out/rom32.offset.auto.h
LegacyBIOS runs correct as if it is the payload.

The difference of post32() and post() is that post32() sets up special
idt, gdt and stack. And post32() would call init_dma() before post().
I will try these work manually. I will write another entry in
LegacyBIOS which will initialize the LegacyBIOS and then return to
coreboot.

By the way, please submit the midterm survay in time. ^_^

Best regards.
Zhang Rui