[coreboot] SMM handling and resident coreboot
jordan.crouse at amd.com
Mon Jul 28 16:24:35 CEST 2008
On 28/07/08 08:27 +0200, Carl-Daniel Hailfinger wrote:
> On 27.07.2008 17:55, ron minnich wrote:
> > On Sun, Jul 27, 2008 at 7:36 AM, Stefan Reinauer <stepan at coresystems.de> wrote:
> >> Since we know how big our RAM is when we copy coreboot to RAM, I suggest
> >> that we copy coreboot to the end of memory and run it from there. It is
> >> a pretty good assumption that no payload will require that space. During
> >> memory map creation, we just reserve 256k at the upper end, and we're good.
> > works for me. I like it.
> AFAICS this means for v3 that we require stage2 to be PIC like initram.
> I'm not entirely happy about that because of possible toolchain issues
> (mostly untested path).
That is part of the growing up process. The v3 model needs to be, above
all things, flexible. Every time we think we have it stable enough,
something new is going to come along and upset that. We will regress many,
many times - the important thing is that the design emerges stronger then
it was before.
Systems Software Development Engineer
Advanced Micro Devices, Inc.
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