[coreboot] Fwd: [newbie] support for GA-M57SLI-S4 and AMD Phenom (K10) possible?
tiagomnm at gmail.com
Tue Jul 29 18:31:15 CEST 2008
---------- Forwarded message ----------
From: Tiago Marques <tiagomnm at gmail.com>
Date: Tue, Jul 29, 2008 at 5:30 PM
Subject: Re: [coreboot] [newbie] support for GA-M57SLI-S4 and AMD
Phenom (K10) possible?
To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Indeed they can. They are using 8Mbit bios chips, with some vendors
managing to cram it all up in 4Mbit, though very, very, few.
On Mon, Jul 28, 2008 at 11:48 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 29.07.2008 00:28, Marc Jones wrote:
>> Marc Jones wrote:
>>> Carl-Daniel Hailfinger wrote:
>>>> On 28.07.2008 22:34, Marc Jones wrote:
>>>>> Peter Stuge wrote:
>>>>>> On Mon, Jul 28, 2008 at 01:13:43PM -0600, Marc Jones wrote:
>>>>>>> There is FAM10 (K10) support in coreboot. The platform would need
>>>>>>> to be ported to the Fam10 code. I would be happy to assist anyone
>>>>>>> who would like to do the port.
>>>>>> Does the Fam10 code also handle K8 or would there be one coreboot
>>>>>> target for m57sli+k8 and one for m57sli+fam10 ?
>>>>> There needs to be one for each. The fam10 code has some significant
>>>> Would it be possible to support both K8 and K10 in one image? I gather
>>>> that the code is not entirely different, so sharing some stuff may be
>>>> The big issue I see is CAR setup. I can code up a version of the CAR
>>>> code which has no ifdefs and handles both family 0Fh and family 10h.
>>>> That depends on whether there's a short code sequence not using too
>>>> registers which can detect family 10h presence. AFAICS CPUID always
>>>> clobbers EAX,EBX,ECX,EDX, so we need to have that sequence quite early
>>>> and store the result somewhere.
>>> The CPUs are socket compatible but they are a generation apart. The
>>> MC, HT and much of the CPU init are different. You would need
>>> complete versions of all the init for both families and the runtime
>>> checking on what path to take. Basically, you have two BIOS in one. I
>>> don't know if that is the right thing to work on but I guess if you
>>> are motivated.... patch away.
>> Hmmm.. We already do two BIOS in one. You could do cpuid detection in
>> a failover image and then choose between a fam10 and a K8 image. It
>> would require some work around the image building and you would still
>> need to do a mainboard port for fam10.
> If I ever tackle that project, I will be doing it for v3 only. Dealing
> with the v2 build system is not my idea of fun.
> I only mentioned the dual family support because it seems vendor BIOSes
> can do it.
> coreboot mailing list
> coreboot at coreboot.org
More information about the coreboot