[coreboot] inteltool is sweet

[Joseph Smith]

Hello,
I finally had a chance to try out inteltool, and it works great! Great job
Stefan! Attached is the output from the Thomson IP1000. Maybe if I get some
free time I will add i82830 northbridge support to it.
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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Intel Northbridge: 8086:3575 (unknown)
Intel Southbridge: 8086:24c0 (ICH4)

============= GPIOS =============

GPIOBASE = 0x0500 (IO)

gpiobase+0x0000: 0x1a003180 (GPIO_USE_SEL)
gpiobase+0x0004: 0x0200ffff (GP_IO_SEL)
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0x1bbf0000 (GP_LVL)
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (GPO_TTL)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (RESERVED)
gpiobase+0x0020: 0x00000000 (RESERVED)
gpiobase+0x0024: 0x00000000 (RESERVED)
gpiobase+0x0028: 0x00000000 (RESERVED)
gpiobase+0x002c: 0x00000000 (GPI_INV)
gpiobase+0x0030: 0x00000fff (GPIO_USE_SEL2)
gpiobase+0x0034: 0x00000000 (GP_IO_SEL2)
gpiobase+0x0038: 0x00000fff (GP_LVL2)
gpiobase+0x003c: 0x00000000 (RESERVED)



============= RCBA ==============

This southbridge does not have RCBA.



============= PMBASE ============

Error: Dumping PMBASE on this southbridge is not (yet) supported.



============= MCHBAR ============

Error: Dumping MCHBAR on this northbridge is not (yet) supported.



============= EPBAR =============

Error: Dumping EPBAR on this northbridge is not (yet) supported.



============= DMIBAR ============

Error: Dumping DMIBAR on this northbridge is not (yet) supported.


========= PCIEXBAR ========

Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.



===================== SHARED MSRs (All Cores) =====================
 MSR 0x00000017 = 0x94910000:0x00000000 (IA32_PLATFORM_ID)
 MSR 0x0000002A = 0x00000000:0xC6440000 (EBL_CR_POWERON)
 (*) MSR 0x000000CD = 0xFFFFFFFF:0xFFFFFFFF (FSB_CLOCK_STS)
 (*) MSR 0x000000CE = 0xFFFFFFFF:0xFFFFFFFF (FSB_CLOCK_VCC)
 (*) MSR 0x000000E2 = 0xFFFFFFFF:0xFFFFFFFF (CLOCK_CST_CONFIG_CONTROL)
 (*) MSR 0x000000E3 = 0xFFFFFFFF:0xFFFFFFFF (PMG_IO_BASE_ADDR)
 (*) MSR 0x000000E4 = 0xFFFFFFFF:0xFFFFFFFF (PMG_IO_CAPTURE_ADDR)
 (*) MSR 0x000000EE = 0xFFFFFFFF:0xFFFFFFFF (EXT_CONFIG)
 MSR 0x0000011E = 0x00000000:0x007447E1 (BBL_CR_CTL3)
 (*) MSR 0x00000194 = 0xFFFFFFFF:0xFFFFFFFF (CLOCK_FLEX_MAX)
 (*) MSR 0x00000198 = 0xFFFFFFFF:0xFFFFFFFF (IA32_PERF_STATUS)
 (*) MSR 0x000001A0 = 0xFFFFFFFF:0xFFFFFFFF (IA32_MISC_ENABLES)
 (*) MSR 0x000001AA = 0xFFFFFFFF:0xFFFFFFFF (PIC_SENS_CFG)
 MSR 0x00000400 = 0x00000000:0xC6440000 (IA32_MC0_CTL)
 MSR 0x00000401 = 0x10000000:0x00000000 (IA32_MC0_STATUS)
 MSR 0x00000402 = 0x00000000:0x00000000 (IA32_MC0_ADDR)
 MSR 0x0000040C = 0x00000000:0x00000001 (IA32_MC4_CTL)
 MSR 0x0000040D = 0x00000000:0x00000000 (IA32_MC4_STATUS)
 (*) MSR 0x0000040E = 0xFFFFFFFF:0xFFFFFFFF (IA32_MC4_ADDR)

====================== UNIQUE MSRs  (core 0) ======================
 MSR 0x00000010 = 0x00000293:0xADC16B0A (IA32_TIME_STAMP_COUNTER)
 MSR 0x0000001B = 0x00000000:0xFEE00100 (IA32_APIC_BASE)
 (*) MSR 0x0000003A = 0xFFFFFFFF:0xFFFFFFFF (IA32_FEATURE_CONTROL)
 (*) MSR 0x0000003F = 0xFFFFFFFF:0xFFFFFFFF (IA32_TEMPERATURE_OFFSET)
 MSR 0x0000008B = 0x00000001:0x00000000 (IA32_BIOS_SIGN_ID)
 (*) MSR 0x000000E7 = 0xFFFFFFFF:0xFFFFFFFF (IA32_MPERF)
 (*) MSR 0x000000E8 = 0xFFFFFFFF:0xFFFFFFFF (IA32_APERF)
 MSR 0x000000FE = 0x00000000:0x00000508 (IA32_MTRRCAP)
 MSR 0x0000015F = 0x00000000:0x002400E0 (DTS_CAL_CTRL)
 MSR 0x00000179 = 0x00000000:0x00000005 (IA32_MCG_CAP)
 MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS)
 (*) MSR 0x00000199 = 0xFFFFFFFF:0xFFFFFFFF (IA32_PERF_CONTROL)
 (*) MSR 0x0000019A = 0xFFFFFFFF:0xFFFFFFFF (IA32_CLOCK_MODULATION)
 (*) MSR 0x0000019B = 0xFFFFFFFF:0xFFFFFFFF (IA32_THERM_INTERRUPT)
 (*) MSR 0x0000019C = 0xFFFFFFFF:0xFFFFFFFF (IA32_THERM_STATUS)
 (*) MSR 0x0000019D = 0xFFFFFFFF:0xFFFFFFFF (GV_THERM)
 MSR 0x000001D9 = 0x00000000:0x00000001 (IA32_DEBUGCTL)
 MSR 0x00000200 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE0)
 MSR 0x00000201 = 0x0000000F:0xE0000800 (IA32_MTRR_PHYSMASK0)
 MSR 0x00000202 = 0x00000000:0x20000006 (IA32_MTRR_PHYSBASE1)
 MSR 0x00000203 = 0x0000000F:0xFE000800 (IA32_MTRR_PHYSMASK1)
 MSR 0x00000204 = 0x00000000:0x22000006 (IA32_MTRR_PHYSBASE2)
 MSR 0x00000205 = 0x0000000F:0xFF000800 (IA32_MTRR_PHYSMASK2)
 MSR 0x00000206 = 0x00000000:0x23000006 (IA32_MTRR_PHYSBASE3)
 MSR 0x00000207 = 0x0000000F:0xFF800800 (IA32_MTRR_PHYSMASK3)
 MSR 0x00000208 = 0x00000000:0xF0000001 (IA32_MTRR_PHYSBASE4)
 MSR 0x00000209 = 0x0000000F:0xF8000800 (IA32_MTRR_PHYSMASK4)
 MSR 0x0000020A = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE5)
 MSR 0x0000020B = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK5)
 MSR 0x0000020C = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE6)
 MSR 0x0000020D = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK6)
 MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7)
 MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7)
 MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000)
 MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000)
 MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000)
 MSR 0x00000268 = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_C0000)
 MSR 0x00000269 = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_C8000)
 MSR 0x0000026A = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_D0000)
 MSR 0x0000026B = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_D8000)
 MSR 0x0000026C = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_E0000)
 MSR 0x0000026D = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_E8000)
 MSR 0x0000026E = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_F0000)
 MSR 0x0000026F = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_F8000)
 MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE)

(*) Some MSRs could not be read. The marked values are unreliable.