[coreboot] r628 - in coreboot-v3: . mainboard/amd/norwich mainboard/artecgroup/dbe61 mainboard/artecgroup/dbe62 mainboard/pcengines/alix1c southbridge/amd/cs5536
svn at coreboot.org
svn at coreboot.org
Sat Mar 1 22:33:51 CET 2008
Author: rminnich
Date: 2008-03-01 22:33:51 +0100 (Sat, 01 Mar 2008)
New Revision: 628
Added:
coreboot-v3/mainboard/amd/norwich/irq_tables.h
coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h
coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h
coreboot-v3/mainboard/pcengines/alix1c/irq_tables.h
Removed:
coreboot-v3/mainboard/amd/norwich/irq_tables.c
coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.c
coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.c
coreboot-v3/mainboard/pcengines/alix1c/irq_tables.c
Modified:
coreboot-v3/Makefile
coreboot-v3/mainboard/amd/norwich/Makefile
coreboot-v3/mainboard/artecgroup/dbe62/Makefile
coreboot-v3/mainboard/pcengines/alix1c/Makefile
coreboot-v3/southbridge/amd/cs5536/Makefile
Log:
Factor out write_pirq_routing_table() for all GeodeLX targets.
Compile tested on norwich, alix1c and dbe62. msm800sev is not affected
and dbe61 is broken anyway.
svn is unable to create a valid patch for what I did, so I'll have to
commit this myself. To reproduce, perform the following commands, then
apply the patch:
svn mv mainboard/amd/norwich/irq_tables.c mainboard/amd/norwich/irq_tables.h
svn mv mainboard/pcengines/alix1c/irq_tables.c mainboard/pcengines/alix1c/irq_tables.h
svn mv mainboard/artecgroup/dbe61/irq_tables.c mainboard/artecgroup/dbe61/irq_tables.h
svn mv mainboard/artecgroup/dbe62/irq_tables.c mainboard/artecgroup/dbe62/irq_tables.h
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
tested on alix1c. Boots, USB, graphics, and ethernet all work.
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>
Modified: coreboot-v3/Makefile
===================================================================
--- coreboot-v3/Makefile 2008-03-01 19:12:19 UTC (rev 627)
+++ coreboot-v3/Makefile 2008-03-01 21:33:51 UTC (rev 628)
@@ -85,6 +85,7 @@
COREBOOTINCLUDE := -I$(src) -Iinclude \
-I$(src)/include \
-I$(src)/include/arch/$(ARCH)/ \
+ -I$(src)/mainboard/$(MAINBOARDDIR)/ \
-include $(obj)/config.h \
-include $(obj)/build.h
Modified: coreboot-v3/mainboard/amd/norwich/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/norwich/Makefile 2008-03-01 19:12:19 UTC (rev 627)
+++ coreboot-v3/mainboard/amd/norwich/Makefile 2008-03-01 21:33:51 UTC (rev 628)
@@ -26,7 +26,7 @@
$(src)/southbridge/amd/cs5536/smbus_initram.c \
$(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o
+STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Deleted: coreboot-v3/mainboard/amd/norwich/irq_tables.c
===================================================================
--- coreboot-v3/mainboard/amd/norwich/irq_tables.c 2008-03-01 19:12:19 UTC (rev 627)
+++ coreboot-v3/mainboard/amd/norwich/irq_tables.c 2008-03-01 21:33:51 UTC (rev 628)
@@ -1,141 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright (C) 2007 Advanced Micro Devices, Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License version 2 as
-* published by the Free Software Foundation.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-*/
-
-#include <types.h>
-#include <lib.h>
-#include <console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
-#include <msr.h>
-#include <io.h>
-#include <pirq_routing.h>
-#include <amd_geodelx.h>
-#include "../../../southbridge/amd/cs5536/cs5536.h"
-
-/* Number of slots and devices in the PIR table */
-#define SLOT_COUNT 6
-
-/* Platform IRQs */
-#define PIRQA 11
-#define PIRQB 10
-#define PIRQC 11
-#define PIRQD 10
-
-/* Map */
-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
-
-/*
- * Norwich interrupt wiring.
- *
- * Devices are:
- *
- * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
- * 00:01.1 Graphics device: Advanced Micro Devices [AMD] Geode LX Graphics
- * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
- * 00:0b.0 slot3
- * 00:0c.0 slot4
- * 00:0d.0 slot1
- * 00:0e.0 slot2
- * 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
- * 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
- * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
- * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
- * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
- *
- */
-
-const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE,
- PIRQ_VERSION,
- 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
- 0x00, /* IRQs devoted exclusively to PCI usage */
- 0x100B, /* Vendor */
- 0x002B, /* Device */
- 0, /* Crap (miniport) */
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
- 0x00, /* Checksum */
- {
- /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
- {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
- {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */
- {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */
- {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */
- {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- u16 chipset_irq_map;
- u32 pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
-
- pirtable_end = copy_pirq_routing_table(addr);
-
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
- chipset_irq_map);
- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
-
- pirq_tbl = (struct irq_routing_table *) (addr);
- num_entries = (pirq_tbl->size - 32) / 16;
-
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
- printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
- pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
- for (j = 0; j < 4; j++) {
- printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
- pirq_tbl->slots[i].irq[j].bitmap);
- /* Finds lsb in bitmap to IRQ#. */
- for (k = 0;
- (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))
- && (pirq_tbl->slots[i].irq[j].bitmap != 0);
- k++);
- pirq[j] = k;
- printk(BIOS_DEBUG, "PIRQ: %d\n", k);
- }
-
- /* Bus, device, slots IRQs for {A,B,C,D}. */
- pci_assign_irqs(pirq_tbl->slots[i].bus,
- pirq_tbl->slots[i].devfn >> 3, pirq);
- }
-
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
-}
Copied: coreboot-v3/mainboard/amd/norwich/irq_tables.h (from rev 627, coreboot-v3/mainboard/amd/norwich/irq_tables.c)
===================================================================
--- coreboot-v3/mainboard/amd/norwich/irq_tables.h (rev 0)
+++ coreboot-v3/mainboard/amd/norwich/irq_tables.h 2008-03-01 21:33:51 UTC (rev 628)
@@ -0,0 +1,95 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright (C) 2007 Advanced Micro Devices, Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <pirq_routing.h>
+#include <amd_geodelx.h>
+#include "../../../southbridge/amd/cs5536/cs5536.h"
+
+/* Number of slots and devices in the PIR table */
+#define SLOT_COUNT 6
+
+/* Platform IRQs */
+#define PIRQA 11
+#define PIRQB 10
+#define PIRQC 11
+#define PIRQD 10
+
+/* Map */
+#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+/*
+ * Norwich interrupt wiring.
+ *
+ * Devices are:
+ *
+ * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
+ * 00:01.1 Graphics device: Advanced Micro Devices [AMD] Geode LX Graphics
+ * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
+ * 00:0b.0 slot3
+ * 00:0c.0 slot4
+ * 00:0d.0 slot1
+ * 00:0e.0 slot2
+ * 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
+ * 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
+ * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
+ * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
+ * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
+ *
+ */
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE,
+ PIRQ_VERSION,
+ 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0x00, /* IRQs devoted exclusively to PCI usage */
+ 0x100B, /* Vendor */
+ 0x002B, /* Device */
+ 0, /* Crap (miniport) */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0x00, /* Checksum */
+ {
+ /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
+ {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */
+ {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */
+ {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */
+ {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */
+ }
+};
Deleted: coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.c
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.c 2008-03-01 19:12:19 UTC (rev 627)
+++ coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.c 2008-03-01 21:33:51 UTC (rev 628)
@@ -1,60 +0,0 @@
-/* This file was generated by getpir.c, do not modify!
- (but if you do, please run checkpir on it to verify)
- * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
- *
- * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-
-#include <arch/pirq_routing.h>
-
-#define ID_SLOT_PCI_NET 1 // ThinCan ethernet
-#define ID_SLOT_PCI_RSVD1 2 // reserved entry 1
-#define ID_SLOT_PCI_RSVD3 3 // reserved entry 2
-#define ID_SLOT_PCI_RSVD2 4 // reserved entry 3
-#define ID_EMBED_PCI 0xff // onboard PCI device
-
-// CS5535 PCI INT[A-D] Interrupt Routing lines.
-#define NO_CONNECT 0 // not used
-#define CS_PCI_INTA 1 // PCI INTA
-#define CS_PCI_INTB 2 // PCI INTB
-#define CS_PCI_INTC 3 // PCI INTC
-#define CS_PCI_INTD 4 // PCI INTD
-
-// IRQ bitmap reference line FEDCBA9876543210
-// 0000110000100000b
-#define PCI_IRQ 0xc20 // PCI allowed IRQs here
-
-const struct irq_routing_table intel_irq_routing_table =
-{
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*6, /* there can be total 2 devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
- 0x0800, /* IRQs devoted exclusively to PCI usage */
- 0x1022, /* Vendor */
- 0x208f, /* Device */
- 0x00000000, /* Crap (miniport) */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- // Geode GX3 Host Bridge and VGA Graphics
- {0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
- // Realtek RTL8100/8139 Network Controller
- {0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0},
- // Reserved for future extensions
- {0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0},
- // Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio.
- {0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
- // Reserved for future extensions
- {0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0},
- // Reserved for future extensions
- {0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0}
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr);
-}
Copied: coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h (from rev 627, coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.c)
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h (rev 0)
+++ coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h 2008-03-01 21:33:51 UTC (rev 628)
@@ -0,0 +1,60 @@
+/* This file was generated by getpir.c, do not modify!
+ (but if you do, please run checkpir on it to verify)
+ * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
+ *
+ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#include <arch/pirq_routing.h>
+
+#define ID_SLOT_PCI_NET 1 // ThinCan ethernet
+#define ID_SLOT_PCI_RSVD1 2 // reserved entry 1
+#define ID_SLOT_PCI_RSVD3 3 // reserved entry 2
+#define ID_SLOT_PCI_RSVD2 4 // reserved entry 3
+#define ID_EMBED_PCI 0xff // onboard PCI device
+
+// CS5535 PCI INT[A-D] Interrupt Routing lines.
+#define NO_CONNECT 0 // not used
+#define CS_PCI_INTA 1 // PCI INTA
+#define CS_PCI_INTB 2 // PCI INTB
+#define CS_PCI_INTC 3 // PCI INTC
+#define CS_PCI_INTD 4 // PCI INTD
+
+// IRQ bitmap reference line FEDCBA9876543210
+// 0000110000100000b
+#define PCI_IRQ 0xc20 // PCI allowed IRQs here
+
+const struct irq_routing_table intel_irq_routing_table =
+{
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*6, /* there can be total 2 devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
+ 0x0800, /* IRQs devoted exclusively to PCI usage */
+ 0x1022, /* Vendor */
+ 0x208f, /* Device */
+ 0x00000000, /* Crap (miniport) */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ // Geode GX3 Host Bridge and VGA Graphics
+ {0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
+ // Realtek RTL8100/8139 Network Controller
+ {0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0},
+ // Reserved for future extensions
+ {0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0},
+ // Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio.
+ {0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
+ // Reserved for future extensions
+ {0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0},
+ // Reserved for future extensions
+ {0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0}
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
Modified: coreboot-v3/mainboard/artecgroup/dbe62/Makefile
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe62/Makefile 2008-03-01 19:12:19 UTC (rev 627)
+++ coreboot-v3/mainboard/artecgroup/dbe62/Makefile 2008-03-01 21:33:51 UTC (rev 628)
@@ -25,7 +25,7 @@
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o
+STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Deleted: coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.c
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.c 2008-03-01 19:12:19 UTC (rev 627)
+++ coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.c 2008-03-01 21:33:51 UTC (rev 628)
@@ -1,116 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright (C) 2007 Advanced Micro Devices, Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License version 2 as
-* published by the Free Software Foundation.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-*/
-
-#include <types.h>
-#include <lib.h>
-#include <console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
-#include <msr.h>
-#include <io.h>
-#include <pirq_routing.h>
-#include <amd_geodelx.h>
-#include "../../../southbridge/amd/cs5536/cs5536.h"
-
-
-
-/* Platform IRQs */
-#define PIRQA 10
-#define PIRQB 11
-#define PIRQC 10
-#define PIRQD 11
-
-/* Map */
-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
-
-const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE,
- PIRQ_VERSION,
- 32 + 16 * 5, /* Max. number of devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
- 0x00, /* IRQs devoted exclusively to PCI usage */
- 0x100B, /* Vendor */
- 0x002B, /* Device */
- 0, /* Crap (miniport) */
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
- 0x00, /* Checksum */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
- {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
- {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- u16 chipset_irq_map;
- u32 pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
-
- pirtable_end = copy_pirq_routing_table(addr);
-
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
- chipset_irq_map);
- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
-
- pirq_tbl = (struct irq_routing_table *) (addr);
- num_entries = (pirq_tbl->size - 32) / 16;
-
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
- printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
- pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
- for (j = 0; j < 4; j++) {
- printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
- pirq_tbl->slots[i].irq[j].bitmap);
- /* Finds lsb in bitmap to IRQ#. */
- for (k = 0;
- (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))
- && (pirq_tbl->slots[i].irq[j].bitmap != 0);
- k++);
- pirq[j] = k;
- printk(BIOS_DEBUG, "PIRQ: %d\n", k);
- }
-
- /* Bus, device, slots IRQs for {A,B,C,D}. */
- pci_assign_irqs(pirq_tbl->slots[i].bus,
- pirq_tbl->slots[i].devfn >> 3, pirq);
- }
-
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
-}
Copied: coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h (from rev 627, coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.c)
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h (rev 0)
+++ coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h 2008-03-01 21:33:51 UTC (rev 628)
@@ -0,0 +1,70 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright (C) 2007 Advanced Micro Devices, Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <pirq_routing.h>
+#include <amd_geodelx.h>
+#include "../../../southbridge/amd/cs5536/cs5536.h"
+
+
+
+/* Platform IRQs */
+#define PIRQA 10
+#define PIRQB 11
+#define PIRQC 10
+#define PIRQD 11
+
+/* Map */
+#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE,
+ PIRQ_VERSION,
+ 32 + 16 * 5, /* Max. number of devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0x00, /* IRQs devoted exclusively to PCI usage */
+ 0x100B, /* Vendor */
+ 0x002B, /* Device */
+ 0, /* Crap (miniport) */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0x00, /* Checksum */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
+ {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
+ }
+};
Modified: coreboot-v3/mainboard/pcengines/alix1c/Makefile
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/Makefile 2008-03-01 19:12:19 UTC (rev 627)
+++ coreboot-v3/mainboard/pcengines/alix1c/Makefile 2008-03-01 21:33:51 UTC (rev 628)
@@ -25,7 +25,7 @@
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o
+STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Deleted: coreboot-v3/mainboard/pcengines/alix1c/irq_tables.c
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/irq_tables.c 2008-03-01 19:12:19 UTC (rev 627)
+++ coreboot-v3/mainboard/pcengines/alix1c/irq_tables.c 2008-03-01 21:33:51 UTC (rev 628)
@@ -1,160 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright (C) 2007 Advanced Micro Devices, Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License version 2 as
-* published by the Free Software Foundation.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-*/
-
-#include <types.h>
-#include <lib.h>
-#include <console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
-#include <msr.h>
-#include <io.h>
-#include <pirq_routing.h>
-#include <amd_geodelx.h>
-#include "../../../southbridge/amd/cs5536/cs5536.h"
-
-
-
-/* Platform IRQs */
-#define PIRQA 11
-#define PIRQB 10
-#define PIRQC 11
-#define PIRQD 9
-
-/* Map */
-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
-
-/*
- * ALIX1.C interrupt wiring.
- *
- * Devices are:
- *
- * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
- * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
- * 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
- * 00:0e.0 Network controller: Intersil Corporation Prism 2.5 Wavelan chipset (rev 01)
- * 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
- * 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
- * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
- * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
- * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
- *
- * The only devices that interrupt are:
- *
- * What Device IRQ PIN PIN WIRED TO
- * -------------------------------------------------
- * AES 00:01.2 0a 01 A A
- * 3VPCI 00:0c.0 0a 01 A A
- * eth0 00:0d.0 0b 01 A B
- * mpci 00:0e.0 0a 01 A A
- * usb 00:0f.3 0b 02 B B
- * usb 00:0f.4 0b 04 D D
- * usb 00:0f.5 0b 04 D D
- *
- * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B.
- */
-
-const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE,
- PIRQ_VERSION,
- 32 + 16 * 5, /* Max. number of devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
- 0x00, /* IRQs devoted exclusively to PCI usage */
- 0x100B, /* Vendor */
- 0x002B, /* Device */
- 0, /* Crap (miniport) */
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
- 0x00, /* Checksum */
- {
- /* If you change the number of entries, change IRQ_SLOT_COUNT above! */
-
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-
- /* CPU */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
-
- /* PCI (slot 1) */
- {0x00, (0x0C << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x4, 0x0},
-
- /* On-board ethernet */
- {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
-
- /* Mini PCI (slot 2) */
- {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},
-
- /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
- {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- u16 chipset_irq_map;
- u32 pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
-
- pirtable_end = copy_pirq_routing_table(addr);
-
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
- chipset_irq_map);
- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
-
- pirq_tbl = (struct irq_routing_table *) (addr);
- num_entries = (pirq_tbl->size - 32) / 16;
-
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
- printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
- pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
- for (j = 0; j < 4; j++) {
- printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
- pirq_tbl->slots[i].irq[j].bitmap);
- /* Finds lsb in bitmap to IRQ#. */
- for (k = 0;
- (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))
- && (pirq_tbl->slots[i].irq[j].bitmap != 0);
- k++);
- pirq[j] = k;
- printk(BIOS_DEBUG, "PIRQ: %d\n", k);
- }
-
- /* Bus, device, slots IRQs for {A,B,C,D}. */
- pci_assign_irqs(pirq_tbl->slots[i].bus,
- pirq_tbl->slots[i].devfn >> 3, pirq);
- }
-
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
-}
Copied: coreboot-v3/mainboard/pcengines/alix1c/irq_tables.h (from rev 627, coreboot-v3/mainboard/pcengines/alix1c/irq_tables.c)
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/irq_tables.h (rev 0)
+++ coreboot-v3/mainboard/pcengines/alix1c/irq_tables.h 2008-03-01 21:33:51 UTC (rev 628)
@@ -0,0 +1,103 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright (C) 2007 Advanced Micro Devices, Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <pirq_routing.h>
+
+
+/* Platform IRQs */
+#define PIRQA 11
+#define PIRQB 10
+#define PIRQC 11
+#define PIRQD 9
+
+/* Map */
+#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+/*
+ * ALIX1.C interrupt wiring.
+ *
+ * Devices are:
+ *
+ * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
+ * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
+ * 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
+ * 00:0e.0 Network controller: Intersil Corporation Prism 2.5 Wavelan chipset (rev 01)
+ * 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
+ * 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
+ * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
+ * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
+ * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
+ *
+ * The only devices that interrupt are:
+ *
+ * What Device IRQ PIN PIN WIRED TO
+ * -------------------------------------------------
+ * AES 00:01.2 0a 01 A A
+ * 3VPCI 00:0c.0 0a 01 A A
+ * eth0 00:0d.0 0b 01 A B
+ * mpci 00:0e.0 0a 01 A A
+ * usb 00:0f.3 0b 02 B B
+ * usb 00:0f.4 0b 04 D D
+ * usb 00:0f.5 0b 04 D D
+ *
+ * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B.
+ */
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE,
+ PIRQ_VERSION,
+ 32 + 16 * 5, /* Max. number of devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0x00, /* IRQs devoted exclusively to PCI usage */
+ 0x100B, /* Vendor */
+ 0x002B, /* Device */
+ 0, /* Crap (miniport) */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0x00, /* Checksum */
+ {
+ /* If you change the number of entries, change IRQ_SLOT_COUNT above! */
+
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+
+ /* CPU */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+ /* PCI (slot 1) */
+ {0x00, (0x0C << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x4, 0x0},
+
+ /* On-board ethernet */
+ {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+ /* Mini PCI (slot 2) */
+ {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},
+
+ /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
+ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
+ }
+};
Modified: coreboot-v3/southbridge/amd/cs5536/Makefile
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/Makefile 2008-03-01 19:12:19 UTC (rev 627)
+++ coreboot-v3/southbridge/amd/cs5536/Makefile 2008-03-01 21:33:51 UTC (rev 628)
@@ -23,6 +23,10 @@
STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
+ifeq ($(CONFIG_PIRQ_TABLE),y)
+STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/irq_tables.o
+endif
+
STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o
endif
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