[coreboot] flashrom issues??

[Carl-Daniel Hailfinger]

On 04.03.2008 14:36, joe at smittys.pointclark.net wrote:
> Quoting joe at smittys.pointclark.net:
>
>   
>> Quoting joe at smittys.pointclark.net:
>>
>>     
>>>>> To check this with superiotool I have to be able to dump the
>>>>> "Runtime Registers", this is where the GPIO's are (See the SMSC
>>>>> lpc47m192 datasheet for more info). Currently superiotool does not
>>>>> dump these registers so modifications will be required.
>>>>>           
>>>> I was relying on the new extended superiotool dumping functionality.
>>>> That doesn't exist yet for your superio, so I should have written
>>>> "...can find out with superiotool (once that has GPIO dumping support
>>>> for your superio) and...". Thanks for correcting me.
>>>>
>>>>         
> Well,
> I wasn't able to get a dump of the "Runtime Registers" with  
> superiotool working, but I was able to get a dump of it with the old  
> dd method,

dd method? Can you please tell me the exact command for that? I think 
the extra register dumping for ITE is totally incompatible with the one 
for SMSC which would explain your problems.

> there are alot of differences........maybe one of these  
> GPIO settings is causing my flashrom issue??? It is hard to say  
> without schmatics, but I could always try one register at a time until  
> it works???
>   

Yes. Or set all of them to the factory BIOS values at once and try 
again. Sometimes dependencies between various registers make it 
dangerous to change only a part of the values.

> Thanks - Joe
>
> rm4100
> 00 00 00 00 dc 00 14 0f e7 00 00 00 00 00 00 00
> 02 00 14 0f ce 00 00 00 00 00 00 00 00 00 03 02
> 81 00 00 01 01 01 01 01 01 01 01 01 01 01 00 01
> 01 01 01 05 05 00 00 00 04 01 01 01 01 86 01 05
> 05 05 04 05 04 05 04 01 01 00 00 00 04 d0 00 07
> 00 00 00 00 00 00 00 00 50 ff ff 00 00 00 00 00
>
> coreboot
> 00 00 00 00 d8 00 14 0f 67 00 00 00 00 00 00 00
> 02 00 14 0f c6 00 00 00 00 00 00 00 00 00 03 02
> 81 00 00 01 01 01 01 01 01 01 01 01 01 01 00 02
> 01 01 01 01 01 00 00 05 04 01 01 01 01 01 01 01
> 01 01 00 01 01 01 01 01 01 00 00 00 04 d0 04 23
> 00 00 00 00 00 00 00 00 50 ff ff 00 00 00 00 00
>   

Nice output.

Regards,
Carl-Daniel


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