[coreboot] [PATCH] v3: AMD DB800 support

Tue Mar 4 23:12:05 CET 2008

On 04.03.2008 22:09, Marc Jones wrote:
>> New patch, completely hand-generated, apply checked and compile checked.
>
> I still had some issues getting the patch to apply. It could be my 
> Thunderbird mail reader but you should check. Attaching the file would 
> avoid a mail reader issue.

Patch attached. I use Seamonkey and the patch applied just fine after 
the roundtrip. Sorry for the inconvenience.

> It wouldn't boot all the way into Linux. It seems like there is a IRQ 
> routing since that is where the image stopped. I attached db800 and 
> norwich console output.

Thanks. The IRQ routing was copied straight from v2 so there should be 
no difference in theory.

There are a few things I don't like about the boot log:
> Done pll_reset
> done pll reset
> SMBus WAIT ERROR 13
> SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
>   

All those SMBus error messages. Need to investigate.

> Done cpubug fixes
> done cpu reg init
> done sdram set registers
> SMBus WAIT ERROR 13
> SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
> SMBus WAIT ERROR 13
> SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
> ========== Check present =======================================================
> ========== MODBANKS ============================================================
> ========== FIELDBANKS ==========================================================
> ========== SPDNUMROWS ==========================================================
> ========== SPDBANKDENSITY ======================================================
> ========== BEFORT CTZ ==========================================================
> ========== TEST DIMM SIZE>8 ====================================================
> ========== PAGESIZE ============================================================
> ========== MAXCOLADDR ==========================================================
> ========== RDMSR CF07 ==========================================================
> ========== WRMSR CF07 ==========================================================
> ========== ALL DONE ============================================================
> ========== Check present =======================================================
> SMBus WAIT ERROR 13
> SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
> SMBus WAIT ERROR 13
> SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
> SMBus WAIT ERROR 13
> SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
> SMBus WAIT ERROR 13
> SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
> SMBus WAIT ERROR 13
> SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
> SMBus WAIT ERROR 13
> SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
> SMBus WAIT ERROR 13
> SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
> SMBus WAIT ERROR 13
> SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
> SMBus WAIT ERROR 13
> SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
> done sdram set spd registers
> DRAM controller init done.
> RAM DLL lock
> done sdram enable
> stage1 returns
> run_file returns with 0
> Done RAM init code
>   
[...]
> PCI: scan devfn 0x0 to 0xff
> PCI: devfn 0x0
> pci_scan_get_dev: list is 0x00087eb4, *list is 0x0000b4c0
> pci_scan_get_dev: check dev pci_1_0 
> pci_scan_get_dev: check dev pci_1_0 it has devfn 0x08
> pci_scan_get_dev: check dev pci_15_0 
> pci_scan_get_dev: check dev pci_15_0 it has devfn 0x78
> pci_scan_get_dev: check dev ioport_46 
> pci_scan_get_dev: child ioport_46(IOPORT: 2e) not a pci device: it's type 11
> PCI: pci_scan_bus pci_scan_get_dev returns dev None (no dev in tree yet)
> PCI: devfn 0x0, bad id 0xffffffff
> PCI: pci_scan_bus pci_probe_dev returns dev 0x00000000("�3
9�Gw�g�7޻����E�A�$@FP%\{�Ճl����7B�f��1�
 ��"
> 0{�j����w�{�
�.��4�xH`\)
> PCI: devfn 0x8
>   

And the above points to memory corruption or reading uninitialized 
memory. That's a bug.

> PCI: devfn 0xb, bad id 0xffffffff
> PCI: pci_scan_bus pci_probe_dev returns dev 0x00000000("�3
9�Gw�g�7޻����E�A�$@FP%\{�Ճl����7B�f��1�
 ��"
> 0{�j����w�{�
�.��4�xH`\)
> PCI: devfn 0xc
>   

Same here. And countless repetitions.

> Phase 4: Reading resources...
> Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0
> read_resources: root(Root Device) read_resources bus 0 link: 0
> read_resources: root(Root Device) dtsname cpus have_resources 0 enabled 1
> cpus: Unknown device path type: 0
> read_resources: cpus() missing phase4_read_resources
> read_resources: root(Root Device) dtsname apic_0 have_resources 0 enabled 1
> read_resources: root(Root Device) dtsname domain_0 have_resources 0 enabled 1
> read_resources: domain_0(PCI_DOMAIN: 0000) read_resources bus 0 link: 0
> read_resources: domain_0(PCI_DOMAIN: 0000) dtsname pci_1_0 have_resources 0 enabled 1
> read_resources: "�3
9�Gw�g�7޻����E�A�$@FP%\{�Ճl����7B�f��1�
 ��"
> 0{�j����w�{�
�.��4�xH`\(<null>) read_resources bus 0 link: 0
> read_resources: "�3
9�Gw�g�7޻����E�A�$@FP%\{�Ճl����7B�f��1�
 ��"
> 0{�j����w�{�
�.��4�xH`\(<null>) read_resources bus 0 link: 0 done
> read_resources: domain_0(PCI_DOMAIN: 0000) dtsname dynamic PCI: 00:01.1 have_resources 0 enabled 1
> read_resources: domain_0(PCI_DOMAIN: 0000) dtsname dynamic PCI: 00:01.2 have_resources 0 enabled 1
>   

Similar bug.

> Copying IRQ routing tables to 0x983040x...done.
> Verifing copy of IRQ routing tables at 0x983040x...done
> Checking IRQ routing table consistency...
> check_pirq_routing_table() - irq_routing_table located at: 0x0x000f0000
> /home/marcj/svn/coreboot-v3/arch/x86/pirq_routing.c:    62:check_pirq_routing_table() - checksum is: 0x00 but should be: 0x26
> done.
>   

Ouch. And I claim the table was a straight copy of the v2 db800 table...

Thanks a lot for testing! Could you maybe test v2 db800 as well to check 
IRQ routing tables consistency there?

Fixes for some of the bugs above will come in a separate patch.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/

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