[coreboot] first output: dbe62 and v3

[ron minnich]

attached. It dies and I'm sure it is bad ram settings, but it's a start.

One thing I plan to change pretty soon: power button control can move
from stage1 to stage2, and power button control will be managed in dts
(another dts setting we would NOT want visible in Kconfig; you could
render a board totally unbootable and unrepairable with the wrong
setting. Kconfig should be for settings that are safe to change).

There are other things in stage1 for the lx that we should try to move
to stage 2:
        cs5536_setup_extmsr();
        cs5536_setup_cis_mode();

        msr = rdmsr(GLCP_SYS_RSTPLL);
        if (msr.lo & (0x3f << 26)) {
                /* PLL is already set and we are reboot from PLL reset. */
                return;
        }

        cs5536_setup_idsel();
        cs5536_usb_swapsif();
        cs5536_setup_iobase();
        cs5536_setup_smbus_gpio();
        /* cs5536_enable_smbus(); -- Leave this out for now. */
//      cs5536_setup_power_button();


how much of this do we want managed in stage1? How much is unchanging,
board to board? How much MUST be there? Really, a lot is going on;
what can we leave to stage 2. Power button for sure; what else?

And how do we parameterize this? Just pass in a set of booleans for
those things we wish to control (e.g. smbus).

At this rate, carl-daniel, we may soon have another board for your list.

thanks

ron
p.s. thanks to artecgroup for such great product design and support.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: dbe62
Type: application/octet-stream
Size: 8460 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20080304/a3c84e19/attachment.obj>