[coreboot] v2[PATCH]RCA RM4100 i82830 support
Corey Osgood
corey.osgood at gmail.com
Wed Mar 5 07:30:40 CET 2008
On Tue, Mar 4, 2008 at 11:37 PM, <joe at smittys.pointclark.net> wrote:
> I hate to say it Corey, but this just sends it into an infinite loop.
> Does it make a difference that the onboard memory is located in slot2
> and slot1 is empty? Here is what I have:
>
> Thanks - Joe
Try this instead, IIRC there are 4 DRBs. If it fails to build with too few
registers, I think you can nuke the extra variable and just do multiple
reads to the same location, or else reuse reg32 in place of reg8_2. I'm not
really sure why the previous version failed, it looks sound to me. It might
be interesting to put in some debugging output, to see what's going wrong.
static void do_ram_command(const struct mem_controller *ctrl, uint32_t
command, uint32_t addr_offset)
{
int i;
uint8_t reg8, reg8_2 = 0;
uint32_t reg32;
/* Configure the RAM command. */
reg32 = pci_read_config32(ctrl->d0, DRC);
/* Clear bits 29, 10-8, 6-4. */
reg32 &= 0xdffff88f;
reg32 |= command << 4;
/* If RAM_COMMAND_NORMAL set the refresh mode and IC bit. */
if (command == RAM_COMMAND_NORMAL) {
reg32 |= ((RAM_COMMAND_REFRESH << 8) | (RAM_COMMAND_IC << 29));
}
pci_write_config32(ctrl->d0, DRC, reg32);
/* RAM_COMMAND_NORMAL affects only the memory controller and
doesn't need to be "sent" to the DIMMs. */
/* if (command == RAM_COMMAND_NORMAL) return; */
PRINT_DEBUG(" Sending RAM command 0x");
PRINT_DEBUG_HEX32(reg32);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(0 + addr_offset);
PRINT_DEBUG("\r\n");
/* NOTE: Dual-sided ready */
read32(0 + addr_offset);
for(i = 0; i < 4; i++) {
reg8 = pci_read_config8(ctrl->d0, DRB + i);
if(reg8 != reg8_2) read32(reg8 * 32 * 1024 * 1024); //extra
parentheses aren't necessary
reg8_2 = reg8;
}
}
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