[coreboot] r3183 - in trunk/coreboot-v2/src: include/device southbridge/via/k8t890 southbridge/via/vt8237r
svn at coreboot.org
svn at coreboot.org
Thu Mar 20 22:19:50 CET 2008
Author: ruik
Date: 2008-03-20 22:19:50 +0100 (Thu, 20 Mar 2008)
New Revision: 3183
Added:
trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_bridge.c
Removed:
trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_bridge.c
Modified:
trunk/coreboot-v2/src/include/device/pci_ids.h
trunk/coreboot-v2/src/southbridge/via/k8t890/Config.lb
trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890.h
trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_ctrl.c
trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c
trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_error.c
trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host.c
trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host_ctrl.c
trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_traf_ctrl.c
trunk/coreboot-v2/src/southbridge/via/k8t890/romstrap.inc
trunk/coreboot-v2/src/southbridge/via/vt8237r/Config.lb
Log:
Following patch adds K8M890 support. It initializes the AGP and graphics UMA.
The V-link setup and HT bridge is redone, because VT8237A has it in another
device. So far following combination of chipsets should now work:
K8T890CE + VT8237R
K8M890(CE) + VT8237R
VIA PC1 brige moved to NB code (vt8237r_bridge.c -> k8t890_bridge.c) and
notes about K8M890 support were added.
Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Modified: trunk/coreboot-v2/src/include/device/pci_ids.h
===================================================================
--- trunk/coreboot-v2/src/include/device/pci_ids.h 2008-03-20 20:46:44 UTC (rev 3182)
+++ trunk/coreboot-v2/src/include/device/pci_ids.h 2008-03-20 21:19:50 UTC (rev 3183)
@@ -1145,6 +1145,13 @@
#define PCI_DEVICE_ID_VIA_K8T890CE_4 0x4238
#define PCI_DEVICE_ID_VIA_K8T890CE_5 0x5238
#define PCI_DEVICE_ID_VIA_K8T890CE_7 0x7238
+#define PCI_DEVICE_ID_VIA_K8M890CE_0 0x0336
+#define PCI_DEVICE_ID_VIA_K8M890CE_1 0x1336
+#define PCI_DEVICE_ID_VIA_K8M890CE_2 0x2336
+#define PCI_DEVICE_ID_VIA_K8M890CE_3 0x3336
+#define PCI_DEVICE_ID_VIA_K8M890CE_4 0x4336
+#define PCI_DEVICE_ID_VIA_K8M890CE_5 0x5336
+#define PCI_DEVICE_ID_VIA_K8M890CE_7 0x7336
#define PCI_DEVICE_ID_VIA_K8T890CE_PEG 0xa238
#define PCI_DEVICE_ID_VIA_K8T890CE_PEX0 0xc238
#define PCI_DEVICE_ID_VIA_K8T890CE_PEX1 0xd238
Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/Config.lb
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/k8t890/Config.lb 2008-03-20 20:46:44 UTC (rev 3182)
+++ trunk/coreboot-v2/src/southbridge/via/k8t890/Config.lb 2008-03-20 21:19:50 UTC (rev 3183)
@@ -19,6 +19,7 @@
driver k8t890_ctrl.o
driver k8t890_dram.o
+driver k8t890_bridge.o
driver k8t890_host.o
driver k8t890_host_ctrl.o
driver k8t890_pcie.o
Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890.h 2008-03-20 20:46:44 UTC (rev 3182)
+++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890.h 2008-03-20 21:19:50 UTC (rev 3183)
@@ -32,4 +32,7 @@
#define K8T890_MMCONFIG_MBAR 0x61
#define K8T890_MULTIPLE_FN_EN 0x4f
+/* the FB size in MB (min is 8MB max is 512MB) */
+#define K8M890_FBSIZEMB 64
+
#endif
Added: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_bridge.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_bridge.c (rev 0)
+++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_bridge.c 2008-03-20 21:19:50 UTC (rev 3183)
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+
+static void bridge_enable(struct device *dev)
+{
+ print_debug("B188 device dump\n");
+
+ /* VIA recommends this, sorry no known info. */
+
+ writeback(dev, 0x40, 0x91);
+ writeback(dev, 0x41, 0x40);
+ writeback(dev, 0x43, 0x44);
+ writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet
+ * says it is reserved
+ */
+ writeback(dev, 0x45, 0x3a);
+ writeback(dev, 0x46, 0x88); /* PCI ID lo */
+ writeback(dev, 0x47, 0xb1); /* PCI ID hi */
+
+ /* Bridge control, K8M890 bit 3 should be set to enable VGA on AGP
+ * (Forward VGA compatible memory and I/O cycles )
+ */
+
+ writeback(dev, 0x3e, 0x16);
+ dump_south(dev);
+}
+
+static const struct device_operations bridge_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .enable = bridge_enable,
+ .scan_bus = pci_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver northbridge_driver __pci_driver = {
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T890CE_BR,
+};
Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_ctrl.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_ctrl.c 2008-03-20 20:46:44 UTC (rev 3182)
+++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_ctrl.c 2008-03-20 21:19:50 UTC (rev 3183)
@@ -23,6 +23,70 @@
#include <device/pci_ids.h>
#include <console/console.h>
+/* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
+ * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1)
+ */
+
+static void vt8237r_cfg(struct device *dev, struct device *devsb)
+{
+ u8 regm, regm2, regm3;
+
+ device_t devfun3;
+
+ devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
+
+ if (!devfun3)
+ devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
+
+ pci_write_config8(dev, 0x70, 0xc2);
+
+ /* PCI Control */
+ pci_write_config8(dev, 0x72, 0xee);
+ pci_write_config8(dev, 0x73, 0x01);
+ pci_write_config8(dev, 0x74, 0x24);
+ pci_write_config8(dev, 0x75, 0x0f);
+ pci_write_config8(dev, 0x76, 0x50);
+ pci_write_config8(dev, 0x77, 0x08);
+ pci_write_config8(dev, 0x78, 0x01);
+ /* APIC on HT */
+ pci_write_config8(dev, 0x7c, 0x7f);
+ pci_write_config8(dev, 0x7f, 0x02);
+
+ /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */
+
+ regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */
+ pci_write_config8(dev, 0x57, regm);
+
+ regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */
+ pci_write_config8(dev, 0x61, regm);
+
+ regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */
+ pci_write_config8(dev, 0x62, regm);
+
+ regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */
+ pci_write_config8(dev, 0xe6, regm);
+
+ regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */
+
+ /*
+ * All access bits for 0xE0000-0xEFFFF encode as just 2 bits!
+ * So the NB reg is quite inconsistent, we expect there only 0xff or 0x00,
+ * and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64!
+ */
+ if (regm3 == 0xff)
+ regm3 = 0xc0;
+ else
+ regm3 = 0x0;
+
+ /* Shadow page F + memhole copy */
+ regm = pci_read_config8(devfun3, 0x83);
+ pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F));
+}
+
+
+
/**
* Setup the V-Link for VT8237R, 8X mode.
*
@@ -41,7 +105,8 @@
* V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03
* V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03
*/
-static void ctrl_init_vt8237r(struct device *dev)
+
+static void vt8237r_vlink_init(struct device *dev)
{
u8 reg;
@@ -50,10 +115,6 @@
* sounthbridges (e.g. VT8237A, VT8237S, VT8237 (without plus R)
* and VT8251) a different init code is required.
*/
- device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
- if (!devsb)
- return;
pci_write_config8(dev, 0xb5, 0x88);
pci_write_config8(dev, 0xb6, 0x88);
@@ -78,11 +139,7 @@
pci_write_config8(dev, 0x48, 0xa3);
}
-static void ctrl_enable(struct device *dev)
-{
- u8 regm, regm2, regm3;
- device_t devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
+static void ctrl_init(struct device *dev) {
/* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0]
should to 1 */
@@ -90,64 +147,36 @@
/* C2P Read ACK Return Priority */
/* PCI CFG Address bits[27:24] are used as extended register address
bit[11:8] */
+
pci_write_config8(dev, 0x47, 0x30);
- /* Magic init. This is not well documented :/ */
- pci_write_config8(dev, 0x70, 0xc2);
- /* PCI Control */
- pci_write_config8(dev, 0x72, 0xee);
- pci_write_config8(dev, 0x73, 0x01);
- pci_write_config8(dev, 0x74, 0x24);
- pci_write_config8(dev, 0x75, 0x0f);
- pci_write_config8(dev, 0x76, 0x50);
- pci_write_config8(dev, 0x77, 0x08);
- pci_write_config8(dev, 0x78, 0x01);
- /* APIC on HT */
- pci_write_config8(dev, 0x7c, 0x7f);
- pci_write_config8(dev, 0x7f, 0x02);
+ /* VT8237R specific configuration other SB are done in their own directories */
- /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */
+ device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
+ if (devsb) {
+ vt8237r_vlink_init(dev);
+ vt8237r_cfg(dev, devsb);
+ }
- regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */
- pci_write_config8(dev, 0x57, regm);
-
- regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */
- pci_write_config8(dev, 0x61, regm);
-
- regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */
- pci_write_config8(dev, 0x62, regm);
-
- regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */
- pci_write_config8(dev, 0xe6, regm);
-
- regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */
-
- /*
- * All access bits for 0xE0000-0xEFFFF encode as just 2 bits!
- * So the NB reg is quite inconsistent, we expect there only 0xff or 0x00,
- * and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64!
- */
- if (regm3 == 0xff)
- regm3 = 0xc0;
- else
- regm3 = 0x0;
-
- /* Shadow page F + memhole copy */
- regm = pci_read_config8(devfun3, 0x83);
- pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F));
}
static const struct device_operations ctrl_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .enable = ctrl_enable,
- .init = ctrl_init_vt8237r,
+ .init = ctrl_init,
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver __pci_driver = {
+static const struct pci_driver northbridge_driver_t __pci_driver = {
.ops = &ctrl_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_7,
};
+
+static const struct pci_driver northbridge_driver_m __pci_driver = {
+ .ops = &ctrl_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M890CE_7,
+};
Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c 2008-03-20 20:46:44 UTC (rev 3182)
+++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c 2008-03-20 21:19:50 UTC (rev 3183)
@@ -23,6 +23,8 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
+#include <bitops.h>
+#include "k8t890.h"
static void dram_enable(struct device *dev)
{
@@ -59,10 +61,75 @@
reg = pci_read_config16(dev, 0x88);
reg &= 0xf800;
+ /* The Address Next to the Last Valid DRAM Address */
pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg);
}
-static const struct device_operations dram_ops = {
+static struct resource *resmax;
+
+static void get_memres(void *gp, struct device *dev, struct resource *res)
+{
+ unsigned int *fbsize = (unsigned int *) gp;
+ uint64_t proposed_base = res->base + res->size - *fbsize;
+
+ printk_debug("get_memres: res->base=%llx res->size=%llx %d %d %d\n",
+ res->base, res->size, (res->size > *fbsize),
+ (!(proposed_base & (*fbsize - 1))),
+ (proposed_base < ((uint64_t) 0xffffffff)));
+
+ /* if we fit and also align OK, and must be below 4GB */
+ if ((res->size > *fbsize) && (!(proposed_base & (*fbsize - 1))) &&
+ (proposed_base < ((uint64_t) 0xffffffff) )) {
+ resmax = res;
+ }
+}
+
+
+static void dram_init_fb(struct device *dev)
+{
+ /* Important bits:
+ * Enable the internal GFX bit 7 of reg 0xa1 plus in same reg:
+ * bits 6:4 X fbuffer size will be 2^(X+2) or 100 = 64MB, 101 = 128MB
+ * bits 3:0 BASE [31:28]
+ * reg 0xa0 bits 7:1 BASE [27:21] bit0 enable CPU access
+ */
+ u8 tmp;
+ uint64_t proposed_base;
+ unsigned int fbsize = (K8M890_FBSIZEMB * 1024 * 1024);
+
+ resmax = NULL;
+ search_global_resources(
+ IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
+ get_memres, (void *) &fbsize);
+
+ /* no space for FB */
+ if (!resmax) {
+ printk_err("VIA FB: no space for framebuffer in RAM\n");
+ return;
+ }
+
+ proposed_base = resmax->base + resmax->size - fbsize;
+ resmax->size -= fbsize;
+
+ printk_debug("VIA FB proposed base: %llx\n", proposed_base);
+
+ /* enable UMA but no FB */
+ pci_write_config8(dev, 0xa1, 0x80);
+
+ /* 27:21 goes to 7:1, 0 is enable CPU access */
+ tmp = (proposed_base >> 20) | 0x1;
+ pci_write_config8(dev, 0xa0, tmp);
+
+ /* 31:28 goes to 3:0 */
+ tmp = ((proposed_base >> 28) & 0xf);
+ tmp = ((log2(K8M890_FBSIZEMB) - 2) << 4);
+ tmp |= 0x80;
+ pci_write_config8(dev, 0xa1, tmp);
+
+ /* TODO K8 needs some UMA fine tuning too maybe call some generic routine here? */
+}
+
+static const struct device_operations dram_ops_t = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
@@ -70,8 +137,23 @@
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &dram_ops,
+static const struct device_operations dram_ops_m = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .enable = dram_enable,
+ .init = dram_init_fb,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver northbridge_driver_t __pci_driver = {
+ .ops = &dram_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_3,
};
+
+static const struct pci_driver northbridge_driver_m __pci_driver = {
+ .ops = &dram_ops_m,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M890CE_3,
+};
Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_error.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_error.c 2008-03-20 20:46:44 UTC (rev 3182)
+++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_error.c 2008-03-20 21:19:50 UTC (rev 3183)
@@ -30,6 +30,8 @@
* bit7 - Parity Error/SERR# Report Through NMI
*/
pci_write_config8(dev, 0x58, 0x81);
+
+ /* TODO: enable AGP errors reporting on K8M890 */
}
static const struct device_operations error_ops = {
@@ -40,8 +42,14 @@
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver __pci_driver = {
+static const struct pci_driver northbridge_driver_t __pci_driver = {
.ops = &error_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_1,
};
+
+static const struct pci_driver northbridge_driver_m __pci_driver = {
+ .ops = &error_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M890CE_1,
+};
Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host.c 2008-03-20 20:46:44 UTC (rev 3182)
+++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host.c 2008-03-20 21:19:50 UTC (rev 3183)
@@ -28,9 +28,32 @@
{
/* Multiple function control */
pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
+
}
-static const struct device_operations host_ops = {
+
+static void host_init(struct device *dev)
+{
+ u8 reg;
+
+ /* AGP Capability Header Control */
+ reg = pci_read_config8(dev, 0x4d);
+ reg |= 0x20; /* GART access enabled by either D0F0 Rx90[8] or D1F0 Rx90[8] */
+ pci_write_config8(dev, 0x4d, reg);
+
+ /* GD Output Stagger Delay */
+ reg = pci_read_config8(dev, 0x42);
+ reg |= 0x10; /* AD[31:16] with 1ns */
+ pci_write_config8(dev, 0x42, reg);
+
+ /* AGP Control */
+ reg = pci_read_config8(dev, 0xbc);
+ reg |= 0x20; /* AGP Read Snoop DRAM Post-Write Buffer */
+ pci_write_config8(dev, 0xbc, reg);
+
+}
+
+static const struct device_operations host_ops_t = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
@@ -38,8 +61,23 @@
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &host_ops,
+static const struct device_operations host_ops_m = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .enable = host_enable,
+ .init = host_init,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver northbridge_driver_t __pci_driver = {
+ .ops = &host_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_0,
};
+
+static const struct pci_driver northbridge_driver_m __pci_driver = {
+ .ops = &host_ops_m,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M890CE_0,
+};
Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host_ctrl.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host_ctrl.c 2008-03-20 20:46:44 UTC (rev 3182)
+++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host_ctrl.c 2008-03-20 21:19:50 UTC (rev 3183)
@@ -23,8 +23,10 @@
#include <device/pci_ids.h>
#include <console/console.h>
+/* this may be later merged */
+
/* This fine tunes the HT link settings, which were loaded by ROM strap. */
-static void host_ctrl_enable(struct device *dev)
+static void host_ctrl_enable_k8t890(struct device *dev)
{
dump_south(dev);
@@ -48,6 +50,11 @@
/* Arbitration control 2 */
pci_write_config8(dev, 0xa6, 0x80);
+ /* this will be possibly removed, when I figure out
+ * if the ROM SIP is good, second reason is that the
+ * unknown bits are AGP related, which are dummy on K8T890
+ */
+
writeback(dev, 0xa0, 0x13); /* Bit4 is reserved! */
writeback(dev, 0xa1, 0x8e); /* Some bits are reserved. */
writeback(dev, 0xa2, 0x0e); /* I/O NVRAM base 0xe00-0xeff disabled. */
@@ -78,16 +85,55 @@
dump_south(dev);
}
-static const struct device_operations host_ctrl_ops = {
+/* This fine tunes the HT link settings, which were loaded by ROM strap. */
+static void host_ctrl_enable_k8m890(struct device *dev) {
+
+ /*
+ * Set PCI to HT outstanding requests to 03.
+ * Bit 4 32 AGP ADS Read Outstanding Request Number
+ */
+ pci_write_config8(dev, 0xa0, 0x13);
+
+ /* Disable NVRAM and enable non-posted PCI writes. */
+ pci_write_config8(dev, 0xa1, 0x8e);
+
+ /*
+ * NVRAM I/O base 0xe00-0xeff, but it is disabled.
+ */
+
+ pci_write_config8(dev, 0xa2, 0x0e);
+ /* Arbitration control */
+ pci_write_config8(dev, 0xa5, 0x3c);
+
+ /* Arbitration control 2 */
+ pci_write_config8(dev, 0xa6, 0x82);
+
+}
+
+static const struct device_operations host_ctrl_ops_t = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .enable = host_ctrl_enable,
+ .enable = host_ctrl_enable_k8t890,
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &host_ctrl_ops,
+static const struct device_operations host_ctrl_ops_m = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .enable = host_ctrl_enable_k8m890,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver northbridge_driver_t __pci_driver = {
+ .ops = &host_ctrl_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_2,
};
+
+static const struct pci_driver northbridge_driver_m __pci_driver = {
+ .ops = &host_ctrl_ops_m,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M890CE_2,
+};
Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_traf_ctrl.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_traf_ctrl.c 2008-03-20 20:46:44 UTC (rev 3182)
+++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_traf_ctrl.c 2008-03-20 21:19:50 UTC (rev 3183)
@@ -68,15 +68,15 @@
res->flags = IORESOURCE_MEM;
}
-static void traf_ctrl_enable(struct device *dev)
+static void traf_ctrl_enable_generic(struct device *dev)
{
volatile u32 *apic;
u32 data;
- /* Enable D3F1-D3F3, no device2 redirect, enable just one device behind
+ /* no device2 redirect, enable just one device behind
* bridge device 2 and device 3).
*/
- pci_write_config8(dev, 0x60, 0x88);
+ pci_write_config8(dev, 0x60, 0x08);
/* Will enable MMCONFIG later. */
pci_write_config8(dev, 0x64, 0x23);
@@ -104,16 +104,46 @@
apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24);
}
-static const struct device_operations traf_ctrl_ops = {
+static void traf_ctrl_enable_k8m890(struct device *dev)
+{
+ traf_ctrl_enable_generic(dev);
+}
+
+static void traf_ctrl_enable_k8t890(struct device *dev)
+{
+ u8 reg;
+
+ traf_ctrl_enable_generic(dev);
+
+ /* Enable D3F1-D3F3 */
+ reg = pci_read_config8(dev, 0x60);
+ pci_write_config8(dev, 0x60, 0x80 | reg);
+}
+
+static const struct device_operations traf_ctrl_ops_m = {
.read_resources = apic_mmconfig_read_resources,
.set_resources = mmconfig_set_resources,
.enable_resources = pci_dev_enable_resources,
- .enable = traf_ctrl_enable,
+ .enable = traf_ctrl_enable_k8m890,
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &traf_ctrl_ops,
+static const struct device_operations traf_ctrl_ops_t = {
+ .read_resources = apic_mmconfig_read_resources,
+ .set_resources = mmconfig_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .enable = traf_ctrl_enable_k8t890,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver northbridge_driver_t __pci_driver = {
+ .ops = &traf_ctrl_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_5,
};
+
+static const struct pci_driver northbridge_driver_m __pci_driver = {
+ .ops = &traf_ctrl_ops_m,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M890CE_5,
+};
Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/romstrap.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/k8t890/romstrap.inc 2008-03-20 20:46:44 UTC (rev 3182)
+++ trunk/coreboot-v2/src/southbridge/via/k8t890/romstrap.inc 2008-03-20 21:19:50 UTC (rev 3183)
@@ -20,7 +20,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/* This file constructs the ROM strap table for K8T890. */
+/* This file constructs the ROM strap table for K8T890 and K8M890 */
.section ".romstrap", "a", @progbits
Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/Config.lb
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/Config.lb 2008-03-20 20:46:44 UTC (rev 3182)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/Config.lb 2008-03-20 21:19:50 UTC (rev 3183)
@@ -23,4 +23,3 @@
driver vt8237r_ide.o
driver vt8237r_lpc.o
driver vt8237r_sata.o
-driver vt8237r_bridge.o
Deleted: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_bridge.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_bridge.c 2008-03-20 20:46:44 UTC (rev 3182)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_bridge.c 2008-03-20 21:19:50 UTC (rev 3183)
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License v2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-
-static void bridge_enable(struct device *dev)
-{
- print_debug("B188 device dump\n");
-
- /* VIA recommends this, sorry no known info. */
- writeback(dev, 0x40, 0x91);
- writeback(dev, 0x41, 0x40);
- writeback(dev, 0x43, 0x44);
- writeback(dev, 0x44, 0x31);
- writeback(dev, 0x45, 0x3a);
- writeback(dev, 0x46, 0x88); /* PCI ID lo */
- writeback(dev, 0x47, 0xb1); /* PCI ID hi */
- writeback(dev, 0x3e, 0x16); /* Bridge control */
-
- dump_south(dev);
-}
-
-static const struct device_operations bridge_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .enable = bridge_enable,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = 0,
-};
-
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &bridge_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T890CE_BR,
-};
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