[coreboot] [PATCH] [RFC] v3: CS5536 cleanup
Carl-Daniel Hailfinger
c-d.hailfinger.devel.2006 at gmx.net
Thu May 8 02:12:59 CEST 2008
Hi Ron,
can you review this?
- Clean up Geode companion chip CS5536 code.
- Improve VPCI hiding debug message and add doxygen comments.
- Eliminate a few redundant dev_find_pci_device() calls.
This should be an equivalence transformation.
Build tested on norwich, db800, alix.1c, alix.2c3, dbe62.
No new breakage on dbe61.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Index: LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c
===================================================================
--- LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c (Revision 677)
+++ LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c (Arbeitskopie)
@@ -89,6 +89,28 @@
};
/**
+ * Hide unwanted virtual PCI device.
+ *
+ * @param vpci_devid The bus location of the device to be hidden.
+ * bits 0 -> 1 zero
+ * bits 2 -> 7 target dword within the target function
+ * (zero if we're disabling entire pci devices)
+ * bits 8 -> 10 target function of the device
+ * bits 11 -> 15 target pci device
+ * bits 16 -> 23 pci bus
+ * bits 24 -> 30 reserved and set to zero
+ * bit 31 triggers the config cycle
+ */
+static void hide_vpci(u32 vpci_devid)
+{
+ printk(BIOS_DEBUG, "Hiding VPCI device: 0x%08X (%02x:%02x.%01x)\n",
+ vpci_devid, (vpci_devid >> 16) & 0xff,
+ (vpci_devid >> 11) & 0x1f, (vpci_devid >> 8) & 0x7);
+ outl(vpci_devid + 0x7C, 0xCF8);
+ outl(0xDEADBEEF, 0xCFC);
+}
+
+/**
* Power button setup.
*
* Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which
@@ -175,8 +197,7 @@
static void enable_ide_nand_flash_header(void)
{
/* Tell VSA to use FLASH PCI header. Not IDE header. */
- outl(0x80007A40, 0xCF8);
- outl(0xDEADBEEF, 0xCFC);
+ hide_vpci(0x800079C4);
}
#define RTC_CENTURY 0x32
@@ -240,16 +261,13 @@
*
* @param sb Southbridge config structure.
*/
-static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb)
+static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb,
+ struct device *dev)
{
struct msr msr;
u16 addr = 0;
u32 gpio_addr;
- struct device *dev;
- dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
-
gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
gpio_addr &= ~1; /* Clear I/O bit */
printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr);
@@ -418,11 +436,11 @@
{
u32 *bar;
struct msr msr;
- struct device *dev;
+ struct device *ehci_dev, *otg_dev, *udc_dev;
- dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
+ ehci_dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
- if (dev) {
+ if (ehci_dev) {
/* Serial short detect enable */
msr = rdmsr(USB2_SB_GLD_MSR_CONF);
msr.hi |= USB2_UPPER_SSDEN_SET;
@@ -431,7 +449,7 @@
/* Write to clear diag register. */
wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
- bar = (u32 *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ bar = (u32 *) pci_read_config32(ehci_dev, PCI_BASE_ADDRESS_0);
/* Make HCCPARAMS writable. */
*(bar + IPREG04) |= USB_HCCPW_SET;
@@ -440,10 +458,10 @@
*(bar + HCCPARAMS) = 0x00005012;
}
- dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
+ otg_dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
- if (dev) {
- bar = (u32 *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ if (otg_dev) {
+ bar = (u32 *) pci_read_config32(otg_dev, PCI_BASE_ADDRESS_0);
*(bar + UOCMUX) &= PUEN_SET;
@@ -458,6 +476,8 @@
*(bar + UOCCAP) |= sb->enable_USBP4_overcurrent;
}
+ udc_dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
/* PBz#6466: If the UOC(OTG) device, port 4, is configured as a
* device, then perform the following sequence:
* - Set SD bit in DEVCTRL udc register
@@ -465,32 +485,24 @@
* - Set APU bit in uoc register
*/
if (sb->enable_USBP4_device) {
- dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
- if (dev) {
- bar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ if (udc_dev) {
+ bar = (u32 *)pci_read_config32(udc_dev, PCI_BASE_ADDRESS_0);
*(bar + UDCDEVCTL) |= UDC_SD_SET;
}
- dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
- if (dev) {
- bar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ if (otg_dev) {
+ bar = (u32 *)pci_read_config32(otg_dev, PCI_BASE_ADDRESS_0);
*(bar + UOCCTL) |= PADEN_SET;
*(bar + UOCCAP) |= APU_SET;
}
}
/* Disable virtual PCI UDC and OTG headers. */
- dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
- if (dev)
- pci_write_config32(dev, 0x7C, 0xDEADBEEF);
+ if (udc_dev)
+ pci_write_config32(udc_dev, 0x7C, 0xDEADBEEF);
- dev = dev_find_pci_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
- if (dev)
- pci_write_config32(dev, 0x7C, 0xDEADBEEF);
+ if (otg_dev)
+ pci_write_config32(otg_dev, 0x7C, 0xDEADBEEF);
}
/**
@@ -605,16 +617,6 @@
pci_write_config8(dev, IDE_CFG, ide_cfg);
}
-
-static void hide_vpci(u32 vpci_devid)
-{
- /* Hide unwanted virtual PCI device. */
- printk(BIOS_DEBUG, "Hiding VPCI device: 0x%08X\n",
- vpci_devid);
- outl(vpci_devid + 0x7C, 0xCF8);
- outl(0xDEADBEEF, 0xCFC);
-}
-
/**
* TODO.
*
@@ -635,7 +637,7 @@
setup_i8259();
lpc_init(sb);
- uarts_init(sb);
+ uarts_init(sb, dev);
if (sb->enable_gpio_int_route) {
printk(BIOS_SPEW, "cs5536: call vr_write\n");
More information about the coreboot
mailing list