[coreboot] Geode LX: PLL initialization in coreboot-v2

[llandre]

I'm having some problems about PLL initialization on GeodeLX-based 
custom hardware so I need to understand exactly how this process works. 
I'm using coreboot-v2. As reference I use the DB800 evaluation board.

I can't understand how the GLCP_SYS_RSTPLL register is set on DB800. The 
strapping pins of the DB800 IRQ13,PW0,SUSPA#,GNT#[2:0] are all '0' and 
PW1 is '1'. Before the PLLs are configured, I can see on the console: 
"GLCP_SYS_RSTPLL (4c000014) value is: 000003d7:00001880". The last byte 
0x80 confirms the strapping pins settings, but the PLL multipliers are 
already set (COREMULT = 11, GLIUMULT = 7, COREDIV and GLIUDIV set, so 
CPU freq = 400MHz and memory DDR266). Where are these values set ?

On my hardware, when pll_reset is called, the automatic configuration is 
used. If I try to use the manual configuration (#define ManualConf 1), 
the board hangs after the CPU is reset from pll_reset.



TIA,
llandre

DAVE Electronics System House - R&D Department
web:   http://www.dave.eu
email: r&d2 at dave-tech.it