[coreboot] and/or busybox issue with alix2c3 serial console

[Myles Watson]

> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Roman Yeryomin
> Sent: Tuesday, November 04, 2008 10:39 AM
> To: coreboot at coreboot.org
> Subject: [coreboot] and/or busybox issue with alix2c3 serial console
> 
> I'm experimenting with coreboot (v3) on alix2c3 and still can't get serial
> console working. :( It stops right after kernel is done booting (I can see
> coreboot, filo and kernel messages just fine). I use openWRT but tried
> also
> another busybox based distribution (imedialinux) -- same problem. With
> original tinybios no problem. At the same time I tried voyage linux
> (without
> busybox) with corebooted alix and it has no such problem. It's obvious
> that
> this problem cannot be identified as 100% busybox's (why then it works on
> tinybios?).
> While digging coreboot sources I've noticed that uart initialization is
> done
> twice for this board -- once in /southbridge/amd/cs5536/cs5536.c (based on
> dts config) and second time in /mainboard/pcengines/alix2c3/stage1.c.
> I tried playing with these (and /southbridge/amd/cs5536/stage1.c),
> disabling
> one code or another, but no luck.
> Tried to set MOD bits:
> 
>     msr.lo = (1 << 4) | (1 << 5) | (1 << 6);
>     msr.hi = 0;
>     wrmsr(MDD_UART1_MOD, msr);
> 
> Also no luck.
> Not enabling upper banks, however, makes uart appear in kernel as regular
> 16550A (and not as NS16550):
> 
>     /* Bit 1 = DEVEN (device enable)
>      * Bit 4 = EN_BANKS (allow access to the upper banks)
>      */
>     //msr.lo = (1 << 4) | (1 << 1);
>     msr.lo = 1 << 1;
>     msr.hi = 0;
> 
> So... where should I go now?  I'm really stuck. Begging for help...

We've seen this before on s2892, SimNOW, and other platforms.  Has anyone
ever nailed this down?  I would say that it's definitely not busybox's
problem since you don't get any kernel output at all.  I didn't know where
to look either.

Thanks,
Myles