[coreboot] r3732 - trunk/coreboot-v2/src/southbridge/intel/i82801gx
svn at coreboot.org
svn at coreboot.org
Thu Nov 6 23:23:06 CET 2008
Author: uwe
Date: 2008-11-06 23:23:05 +0100 (Thu, 06 Nov 2008)
New Revision: 3732
Modified:
trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c
Log:
The enable_hpet() code in intel/i82801gx will not work with the
ICH7 southbridge (but it might work with ICH4/ICH5 or so).
The ICH7 needs a different init code. Drop the non-working code for now.
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2008-11-05 22:54:36 UTC (rev 3731)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2008-11-06 22:23:05 UTC (rev 3732)
@@ -194,22 +194,7 @@
static void enable_hpet(struct device *dev)
{
- u32 reg32;
- u32 code = (0 & 0x3);
-
- reg32 = pci_read_config32(dev, GEN_CNTL);
- reg32 |= (1 << 17); /* Enable HPET. */
- /*
- * Bits [16:15] Memory Address Range
- * 00 FED0_0000h - FED0_03FFh
- * 01 FED0_1000h - FED0_13FFh
- * 10 FED0_2000h - FED0_23FFh
- * 11 FED0_3000h - FED0_33FFh
- */
- reg32 &= ~(3 << 15); /* Clear it */
- reg32 |= (code << 15);
- /* TODO: reg32 is never written to anywhere? */
- printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
+ /* TODO */
}
static void i82801gx_lock_smm(struct device *dev)
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