[coreboot] Resource allocation

[Marc Jones]

----- Original Message ----
> From: Myles Watson <mylesgw at gmail.com>
> To: Coreboot <coreboot at coreboot.org>
> Sent: Monday, November 10, 2008 2:53:57 PM
> Subject: [coreboot] Resource allocation
> 
> I need to clear up my understanding of resource allocation.  Here's my
> understanding of it:
> 
> 1. Start at the root with 2 resources (1 for memory, 1 for IO)
> 2. For each child of each link:
>     A. Add resources
>     B. Get common constraints
>     C. Descend links
>     D. Propagate back to root
> 
> When you're done you should have the Root device with the superset of all
> devices' resources.
> 

Yes, and each bridge needs the resources grouped which is why the links(bridges) are desended as found.

> My question is if resources ever split.  In other words, lets imagine a
> device which implements several IO ports in the 0x3fX range and larger
> regions that must be mapped above 0x1000.  Since the limit for the smaller
> regions is 0x7ff and the alignment for the larger regions is 0x1000, they
> both can't coexist.
> 
> What happens?

Everything
below 0x1000 is legacy IO space and are not typically used by PCI
devices (some devices/firmware sneek some stuff in around 0x800 for
ACPI). As you noted there are some devices that might need to decode
legacy regions to boot. If that is the case they will usually have a
legacy enable bit in the header. In legacy mode the PCI BARs are
ignored. The firmware, option ROM, and driver need to be aware of which
mode it is in. An example is the AMD sb600 IDE controller(Device 20,
Function 1). There is a legacy/PCI mode in the revision register ot
offset 0x8.

http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf


Marc