[coreboot] r994 - in coreboot-v3: . arch/x86 mainboard southbridge/intel/i82801gx

[svn at coreboot.org]

Author: rminnich
Date: 2008-11-12 01:38:13 +0100 (Wed, 12 Nov 2008)
New Revision: 994

Modified:
   coreboot-v3/Kconfig
   coreboot-v3/arch/x86/Kconfig
   coreboot-v3/mainboard/Kconfig
   coreboot-v3/southbridge/intel/i82801gx/Makefile
Log:
Filling in core 2 support. 

This actually starts to get compile errors, instead of config errors. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/Kconfig
===================================================================
--- coreboot-v3/Kconfig	2008-11-12 00:22:42 UTC (rev 993)
+++ coreboot-v3/Kconfig	2008-11-12 00:38:13 UTC (rev 994)
@@ -114,6 +114,8 @@
 	boolean
 config SOUTHBRIDGE_VIA_VT8237
 	boolean
+config SOUTHBRIDGE_INTEL_I82801GX
+	boolean
 
 # Super I/Os:
 config SUPERIO_WINBOND_W83627HF

Modified: coreboot-v3/arch/x86/Kconfig
===================================================================
--- coreboot-v3/arch/x86/Kconfig	2008-11-12 00:22:42 UTC (rev 993)
+++ coreboot-v3/arch/x86/Kconfig	2008-11-12 00:38:13 UTC (rev 994)
@@ -56,6 +56,14 @@
 	  arch/x86/Makefile for more hints on possible values.
 	  It is usually set in mainboard/*/Kconfig.
 
+config CPU_INTEL_CORE2
+	boolean
+	help
+	  CPU type. At the moment this option selects the reset vector and
+	  Cache-as-RAM (CAR) implementation for a mainboard. See
+	  arch/x86/Makefile for more hints on possible values.
+	  It is usually set in mainboard/*/Kconfig.
+
 config CPU_VIA_C7
 	boolean
 	help
@@ -102,6 +110,7 @@
 config LOGICAL_CPUS
 	hex
 	depends CPU_AMD_K8
+	depends CPU_INTEL_CORE2
 	default 1
 	help
 	  How many logical CPUs there are. FIXME.
@@ -157,7 +166,7 @@
 
 config IOAPIC
 	boolean
-	depends ARCH_X86 && CPU_AMD_K8
+	depends ARCH_X86 && CPU_AMD_K8 || CPU_INTEL_CORE2
 	default 0
 	help
 	  If you want to configure an IOAPIC, set this.
@@ -168,6 +177,7 @@
 	default 0x80000 if CPU_AMD_GEODELX
 	default 0xc8000 if CPU_AMD_K8
 	default 0xffef0000 if CPU_VIA_C7
+	default 0xffef0000 if CPU_INTEL_CORE2
 	help
 	  This option sets the base address of the area used for CAR.
 
@@ -177,6 +187,7 @@
 	default 0x8000 if CPU_AMD_GEODELX
 	default 0x8000 if CPU_AMD_K8
 	default 0x8000 if CPU_VIA_C7
+	default 0x8000 if CPU_INTEL_CORE2
 	help
 	  This option sets the size of the area used for CAR.
 
@@ -186,6 +197,7 @@
 	default 0x1000 if CPU_AMD_GEODELX
 	default 0x2000 if CPU_AMD_K8
 	default 0x1000 if CPU_VIA_C7
+	default 0x1000 if CPU_INTEL_CORE2
 	help
 	  This option sets the top of the memory area, in KiB,
 	  used for coreboot.

Modified: coreboot-v3/mainboard/Kconfig
===================================================================
--- coreboot-v3/mainboard/Kconfig	2008-11-12 00:22:42 UTC (rev 993)
+++ coreboot-v3/mainboard/Kconfig	2008-11-12 00:38:13 UTC (rev 994)
@@ -58,6 +58,11 @@
 	help
 	  Select this option for systems from Jetway.
 
+config VENDOR_KONTRON
+	bool "Kontron"
+	help
+	  Select this option for systems from Kontron.
+
 config VENDOR_EMULATION
 	bool "Emulated systems"
 	help
@@ -82,6 +87,7 @@
 source "mainboard/emulation/Kconfig"
 source "mainboard/gigabyte/Kconfig"
 source "mainboard/jetway/Kconfig"
+source "mainboard/kontron/Kconfig"
 source "mainboard/pcengines/Kconfig"
 source "mainboard/via/Kconfig"
 

Modified: coreboot-v3/southbridge/intel/i82801gx/Makefile
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/Makefile	2008-11-12 00:22:42 UTC (rev 993)
+++ coreboot-v3/southbridge/intel/i82801gx/Makefile	2008-11-12 00:38:13 UTC (rev 994)
@@ -19,7 +19,7 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB600),y)
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y)
 
 STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82801gx/i82801gx.c