[coreboot] [PATCH] flashrom: Make ICH SPI flash chip read more resilient

[Carl-Daniel Hailfinger]

Currently flashrom assumes every vendor BIOS shares our view about which
SPI opcodes should be placed in which location. Move to a less
optimistic implementation and actually use the generic SPI read
functions. They're useful for abstracting exactly this stuff and that
makes them the preferred choice.

This patch depends on the patch with improved SPI error checking.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-ich_spi_generalize/ichspi.c
===================================================================
--- flashrom-ich_spi_generalize/ichspi.c	(Revision 3754)
+++ flashrom-ich_spi_generalize/ichspi.c	(Arbeitskopie)
@@ -300,7 +300,7 @@
 	if (op.atomic != 0) {
 		/* Select atomic command */
 		temp16 |= SPIC_ACS;
-		/* Selct prefix opcode */
+		/* Select prefix opcode */
 		if ((op.atomic - 1) == 1) {
 			/*Select prefix opcode 2 */
 			temp16 |= SPIC_SPOP;
@@ -491,19 +491,15 @@
 	for (a = 0; a < page_size; a += maxdata) {
 		if (remaining < maxdata) {
 
-			if (run_opcode
-			    (curopcodes->opcode[1],
-			     offset + (page_size - remaining), remaining,
-			     &buf[page_size - remaining]) != 0) {
+			if (spi_nbyte_read(offset + (page_size - remaining),
+				&buf[page_size - remaining], remaining)) {
 				printf_debug("Error reading");
 				return 1;
 			}
 			remaining = 0;
 		} else {
-			if (run_opcode
-			    (curopcodes->opcode[1],
-			     offset + (page_size - remaining), maxdata,
-			     &buf[page_size - remaining]) != 0) {
+			if (spi_nbyte_read(offset + (page_size - remaining),
+				&buf[page_size - remaining], maxdata)) {
 				printf_debug("Error reading");
 				return 1;
 			}


-- 
http://www.hailfinger.org/

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