[coreboot] How to find out "page size" of a flash chip?
FENG Yu Ning
fengyuning1984 at gmail.com
Wed Nov 19 14:18:43 CET 2008
On 11/19/08, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On ICH SPI, page_size is the maximum number of bytes you can write and
> read in one operation. ICH SPI hardcodes eraseblock size to 4k. ITE SPI
> is different.
Point me to the exact place of documentation if convenient? I have
been reading(quick browsing) the ICH7 spec., but have not found this
limitation yet(or just forgotten immediately). I have been reading
various docs these days.
> I sent a patch to use explicit erase block sizes, but that patch does
> not have any Ack yet.
About when? Maybe I can help search for it.
BTW, I have not finished reading ichspi.c, but ask previously, are we
able to write a part of the chip in ichspi.c(to support ROM layout)?
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