[coreboot] r1051 - in coreboot-v3: mainboard/kontron/986lcd-m northbridge/intel/i945 southbridge/intel/i82801gx

[svn at coreboot.org]

Author: rminnich
Date: 2008-11-24 23:20:48 +0100 (Mon, 24 Nov 2008)
New Revision: 1051

Modified:
   coreboot-v3/mainboard/kontron/986lcd-m/dts
   coreboot-v3/northbridge/intel/i945/bus.dts
   coreboot-v3/northbridge/intel/i945/northbridge.c
   coreboot-v3/southbridge/intel/i82801gx/smi.c
Log:
This board now builds. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/mainboard/kontron/986lcd-m/dts
===================================================================
--- coreboot-v3/mainboard/kontron/986lcd-m/dts	2008-11-24 21:15:19 UTC (rev 1050)
+++ coreboot-v3/mainboard/kontron/986lcd-m/dts	2008-11-24 22:20:48 UTC (rev 1051)
@@ -147,7 +147,6 @@
 		/config/("northbridge/intel/i945/northbridge.dts");
 		/* guesses; we need a real lspci */
 			pci at 0,0 {
-			/config/("northbridge/intel/i945/bus.dts");
 				pci at 1b,0 {
 					/config/("southbridge/intel/i82801gx/ac97audio.dts");
 				};

Modified: coreboot-v3/northbridge/intel/i945/bus.dts
===================================================================
--- coreboot-v3/northbridge/intel/i945/bus.dts	2008-11-24 21:15:19 UTC (rev 1050)
+++ coreboot-v3/northbridge/intel/i945/bus.dts	2008-11-24 22:20:48 UTC (rev 1051)
@@ -18,5 +18,5 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 {
-	device_operations	= "i945_bus_ops";
+	device_operations	= "i945_cpu_bus_ops";
 };

Modified: coreboot-v3/northbridge/intel/i945/northbridge.c
===================================================================
--- coreboot-v3/northbridge/intel/i945/northbridge.c	2008-11-24 21:15:19 UTC (rev 1050)
+++ coreboot-v3/northbridge/intel/i945/northbridge.c	2008-11-24 22:20:48 UTC (rev 1051)
@@ -164,7 +164,7 @@
 		i945_ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
 	}
 
-	assign_resources(&dev->link[0]);
+	phase4_assign_resources(&dev->link[0]);
 }
 
 static unsigned int i945_pci_domain_scan_bus(struct device * dev, unsigned int max)
@@ -189,6 +189,7 @@
 	.phase5_enable_resources = enable_childrens_resources,
 	.phase6_init		 = NULL,
 	.ops_pci		 = &pci_dev_ops_pci,
+	.ops_pci_bus      = &pci_cf8_conf1,	/* Do we want to use the memory mapped space here? */
 };
 
 static void mc_read_resources(struct device * dev)
@@ -230,14 +231,14 @@
 	pci_set_resources(dev);
 }
 
-static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device)
+static void i945_set_subsystem(struct device * dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
 static struct pci_operations intel_pci_ops = {
-	.set_subsystem    = intel_set_subsystem,
+	.set_subsystem    = i945_set_subsystem,
 };
 
 struct device_operations i945_mc_ops = {
@@ -265,7 +266,7 @@
 }
 
 #warning get a number of the 945 mc
-struct device_operations i945_cpu_ops = {
+struct device_operations i945_cpu_bus_ops = {
 	.id = {.type = DEVICE_ID_PCI,
 		{.pci = {.vendor = PCI_VENDOR_ID_INTEL,
 			      .device = 0x1233}}},

Modified: coreboot-v3/southbridge/intel/i82801gx/smi.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/smi.c	2008-11-24 21:15:19 UTC (rev 1050)
+++ coreboot-v3/southbridge/intel/i82801gx/smi.c	2008-11-24 22:20:48 UTC (rev 1051)
@@ -306,7 +306,7 @@
 	outb(0x00, 0xb2);
 }
 
-void smm_install(void)
+void smm_install(void *smm, unsigned int smm_len)
 {
 	/* enable the SMM memory window */
 	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
@@ -321,10 +321,10 @@
 			G_SMRAME | C_BASE_SEG);
 }
 
-void smm_init(void)
+void smm_init(void *smm, unsigned int smm_len)
 {
 	smm_relocate();
-	smm_install();
+	smm_install(smm, smm_len);
 }
 
 void smm_lock(void)