[coreboot] r893 - in coreboot-v3/southbridge/amd: rs690 sb600
svn at coreboot.org
svn at coreboot.org
Mon Oct 6 19:12:38 CEST 2008
Author: rminnich
Date: 2008-10-06 19:12:38 +0200 (Mon, 06 Oct 2008)
New Revision: 893
Added:
coreboot-v3/southbridge/amd/rs690/Makefile
coreboot-v3/southbridge/amd/sb600/Makefile
Modified:
coreboot-v3/southbridge/amd/rs690/cmn.c
coreboot-v3/southbridge/amd/rs690/gfx.c
coreboot-v3/southbridge/amd/rs690/ht.c
coreboot-v3/southbridge/amd/rs690/pcie.c
coreboot-v3/southbridge/amd/rs690/rs690.c
coreboot-v3/southbridge/amd/rs690/rs690.h
coreboot-v3/southbridge/amd/rs690/stage1.c
coreboot-v3/southbridge/amd/sb600/hda.c
coreboot-v3/southbridge/amd/sb600/hda.dts
coreboot-v3/southbridge/amd/sb600/ide.c
coreboot-v3/southbridge/amd/sb600/lpc.c
coreboot-v3/southbridge/amd/sb600/pci.c
coreboot-v3/southbridge/amd/sb600/sata.c
coreboot-v3/southbridge/amd/sb600/sb600.c
coreboot-v3/southbridge/amd/sb600/sb600.h
coreboot-v3/southbridge/amd/sb600/sb600_smbus.h
coreboot-v3/southbridge/amd/sb600/sm.c
coreboot-v3/southbridge/amd/sb600/stage1.c
coreboot-v3/southbridge/amd/sb600/stage1_reset.c
coreboot-v3/southbridge/amd/sb600/usb.c
Log:
This sb600 and rs690 support for a dbm690t that compiles. Stage0 is
23K, too large.
dbe62 was tested and works i.e. this does no harm.
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Added: coreboot-v3/southbridge/amd/rs690/Makefile
===================================================================
--- coreboot-v3/southbridge/amd/rs690/Makefile (rev 0)
+++ coreboot-v3/southbridge/amd/rs690/Makefile 2008-10-06 17:12:38 UTC (rev 893)
@@ -0,0 +1,33 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 coresystems GmbH
+## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS690),y)
+
+STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/rs690/cmn.c \
+ $(src)/southbridge/amd/rs690/gfx.c \
+ $(src)/southbridge/amd/rs690/ht.c \
+ $(src)/southbridge/amd/rs690/pcie.c \
+ $(src)/southbridge/amd/rs690/rs690.c
+
+STAGE0_CHIPSET_SRC += $(src)/southbridge/amd/rs690/stage1.c
+
+
+endif
Modified: coreboot-v3/southbridge/amd/rs690/cmn.c
===================================================================
--- coreboot-v3/southbridge/amd/rs690/cmn.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/rs690/cmn.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -48,9 +48,9 @@
/*get BAR3 base address for nbcfg0x1c */
u32 addr = pci_read_config32(nb_dev, 0x1c);
printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
- dev->path.u.pci.devfn);
+ dev->path.pci.devfn);
addr |= dev->bus->secondary << 20 | /* bus num */
- dev->path.u.pci.devfn << 12 | reg;
+ dev->path.pci.devfn << 12 | reg;
return *((u32 *) addr);
}
@@ -61,9 +61,9 @@
/*get BAR3 base address for nbcfg0x1c */
u32 addr = pci_read_config32(nb_dev, 0x1c);
printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
- dev->path.u.pci.devfn);
+ dev->path.pci.devfn);
addr |= dev->bus->secondary << 20 | /* bus num */
- dev->path.u.pci.devfn << 12 | reg_pos;
+ dev->path.pci.devfn << 12 | reg_pos;
reg = reg_old = *((u32 *) addr);
reg &= ~mask;
@@ -244,7 +244,7 @@
{
u16 count = 5000;
u32 lc_state, reg;
- int8_t current, res = 0;
+ u8 current, res = 0;
while (count--) {
mdelay(40);
@@ -304,6 +304,7 @@
*/
void rs690_set_tom(struct device * nb_dev)
{
+ extern unsigned long uma_memory_start;
/* set TOM */
pci_write_config32(nb_dev, 0x90, uma_memory_start);
nbmc_write_index(nb_dev, 0x1e, uma_memory_start);
Modified: coreboot-v3/southbridge/amd/rs690/gfx.c
===================================================================
--- coreboot-v3/southbridge/amd/rs690/gfx.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/rs690/gfx.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -76,7 +76,7 @@
static void internal_gfx_pci_dev_init(struct device *dev)
{
unsigned short deviceid, vendorid;
- struct southbridge_amd_rs690_gfx_dts_config *cfg = dev->device_configuration;
+ struct southbridge_amd_rs690_gfx_config *cfg = dev->device_configuration;
deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x, vga_rom_address=0x%x.\n",
@@ -126,10 +126,10 @@
{
u32 l_dword;
int i;
- struct device * k8_f0 = 0, k8_f2 = 0;
+ struct device * k8_f0 = 0, *k8_f2 = 0;
struct device * nb_dev = dev_find_slot(0, 0);
- printk(BIOS_INFO, "rs690_internal_gfx_enable dev=0x%x, nb_dev=0x%x.\n", dev,
+ printk(BIOS_INFO, "rs690_internal_gfx_enable dev=%p, nb_dev=%p.\n", dev,
nb_dev);
/* set APERTURE_SIZE, 128M. */
@@ -214,7 +214,7 @@
{
u8 result, width;
u32 reg32;
- struct southbridge_amd_rs690_gfx_dts_config *cfg = nb_dev->device_configuration;
+ struct southbridge_amd_rs690_gfx_config *cfg = nb_dev->device_configuration;
printk(BIOS_INFO, "rs690_gfx_init single_port_configuration.\n");
@@ -271,8 +271,7 @@
{
u8 result, width;
u32 reg32;
- struct southbridge_amd_rs690_config *cfg =
- (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+ struct southbridge_amd_rs690_gfx_config *cfg = nb_dev->device_configuration;
/* step 15: Training for Device 2 */
set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
@@ -350,8 +349,7 @@
{
u32 reg32;
struct device * sb_dev;
- struct southbridge_amd_rs690_config *cfg =
- (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+ struct southbridge_amd_rs690_gfx_config *cfg = nb_dev->device_configuration;
/* step 5.9.1.1 */
reg32 = nbpcie_p_read_index(dev, 0xa2);
@@ -395,10 +393,9 @@
void rs690_gfx_init(struct device * nb_dev, struct device * dev, u32 port)
{
u16 reg16;
- struct southbridge_amd_rs690_config *cfg =
- (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+ struct southbridge_amd_rs690_gfx_config *cfg = nb_dev->device_configuration;
- printk(BIOS_INFO, "rs690_gfx_init, nb_dev=0x%x, dev=0x%x, port=0x%x.\n",
+ printk(BIOS_INFO, "rs690_gfx_init, nb_dev=%p dev=%p, port=0x%x.\n",
nb_dev, dev, port);
/* step 0, REFCLK_SEL, skip A11 revision */
@@ -572,7 +569,7 @@
{.pci = {.vendor = PCI_VENDOR_ID_ATI,
.device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX}}},
.constructor = default_device_constructor,
- .phase2_setup_scanbus = rs690_internal_gfx_enable,
+ .phase2_setup_scan_bus = rs690_internal_gfx_enable,
.phase3_scan = 0,
.phase4_read_resources = rs690_gfx_read_resources,
.phase4_set_resources = rs690_gfx_set_resources,
Modified: coreboot-v3/southbridge/amd/rs690/ht.c
===================================================================
--- coreboot-v3/southbridge/amd/rs690/ht.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/rs690/ht.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -78,11 +78,14 @@
.set_subsystem = pci_dev_set_subsystem,
};
-struct device_operations rs690_gfx = {
+void rs690_enable(struct device * dev);
+
+struct device_operations rs690_ht = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_ATI,
.device = PCI_DEVICE_ID_ATI_RS690_HT}}},
.constructor = default_device_constructor,
+ .phase2_setup_scan_bus = rs690_enable,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
Modified: coreboot-v3/southbridge/amd/rs690/pcie.c
===================================================================
--- coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -51,10 +51,10 @@
0 /* GppPwr */
};
-static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port);
-static void ValidatePortEn(device_t nb_dev);
+static void PciePowerOffGppPorts(struct device * nb_dev, struct device * dev, u32 port);
+static void ValidatePortEn(struct device * nb_dev);
-static void ValidatePortEn(device_t nb_dev)
+static void ValidatePortEn(struct device * nb_dev)
{
}
@@ -63,11 +63,11 @@
* Compliant with CIM_33's PCIEPowerOffGppPorts
* Power off unused GPP lines
*****************************************************************/
-static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
+static void PciePowerOffGppPorts(struct device * nb_dev, struct device * dev, u32 port)
{
u32 reg;
u16 state_save;
- struct southbridge_amd_rs690_pcie_dts_config *cfg = nb_dev->device_configuration;
+ struct southbridge_amd_rs690_pcie_config *cfg = nb_dev->device_configuration;
u8 state = cfg->port_enable;
if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS))
@@ -109,7 +109,7 @@
/* Enable pci error detecting */
u32 dword;
- printk_debug("pcie_init in rs690_pcie.c\n");
+ printk(BIOS_DEBUG, "pcie_init in rs690_pcie.c\n");
/* System error enable */
dword = pci_read_config32(dev, 0x04);
@@ -121,10 +121,10 @@
/**********************************************************************
**********************************************************************/
-static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
+static void switching_gpp_configurations(struct device * nb_dev, struct device * sb_dev)
{
u32 reg;
- struct southbridge_amd_rs690_pcie_dts_config *cfg = nb_dev->device_configuration;
+ struct southbridge_amd_rs690_pcie_config *cfg = nb_dev->device_configuration;
/* enables GPP reconfiguration */
reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
@@ -165,9 +165,9 @@
* The rs690 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration
* Space to a 256MB range within the first 4GB of addressable memory.
*****************************************************************/
-void enable_pcie_bar3(device_t nb_dev)
+void enable_pcie_bar3(struct device * nb_dev)
{
- printk_debug("enable_pcie_bar3()\n");
+ printk(BIOS_DEBUG, "enable_pcie_bar3()\n");
set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */
set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16);
@@ -181,9 +181,9 @@
* We should disable bar3 when we want to exit rs690_enable, because bar3 will be
* remapped in set_resource later.
*****************************************************************/
-void disable_pcie_bar3(device_t nb_dev)
+void disable_pcie_bar3(struct device * nb_dev)
{
- printk_debug("disable_pcie_bar3()\n");
+ printk(BIOS_DEBUG, "disable_pcie_bar3()\n");
set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */
pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */
ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
@@ -198,13 +198,13 @@
* port:
* p2p bridge number, 4-8
*****************************************/
-void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
+void rs690_gpp_sb_init(struct device * nb_dev, struct device * dev, u32 port)
{
u8 reg8;
u16 reg16;
- device_t sb_dev;
- struct southbridge_amd_rs690_pcie_dts_config *cfg = nb_dev->device_configuration;
- printk_debug("gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev, dev, port);
+ struct device * sb_dev;
+ struct southbridge_amd_rs690_pcie_config *cfg = nb_dev->device_configuration;
+ printk(BIOS_DEBUG, "gpp_sb_init nb_dev=%p, dev=%p, port=0x%x\n", nb_dev, dev, port);
/* init GPP core */
set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8,
@@ -260,7 +260,7 @@
PcieReleasePortTraining(nb_dev, dev, port);
if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) {
u8 res = PcieTrainPort(nb_dev, dev, port);
- printk_debug("PcieTrainPort port=0x%x result=%d\n", port, res);
+ printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res);
if (res) {
AtiPcieCfg.PortDetect |= 1 << port;
}
@@ -331,10 +331,10 @@
/*****************************************
* Compliant with CIM_33's PCIEConfigureGPPCore
*****************************************/
-void config_gpp_core(device_t nb_dev, device_t sb_dev)
+void config_gpp_core(struct device * nb_dev, struct device * sb_dev)
{
u32 reg;
- struct southbridge_amd_rs690_pcie_dts_config *cfg = nb_dev->chip_info;
+ struct southbridge_amd_rs690_pcie_config *cfg = nb_dev->device_configuration;
reg = nbmisc_read_index(nb_dev, 0x20);
if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP)
@@ -352,10 +352,9 @@
/*****************************************
* Compliant with CIM_33's PCIEMiscClkProg
*****************************************/
-void pcie_config_misc_clk(device_t nb_dev)
+void pcie_config_misc_clk(struct device * nb_dev)
{
u32 reg;
- struct bus pbus; /* fake bus for dev0 fun1 */
reg = pci_read_config32(nb_dev, 0x4c);
reg |= 1 << 0;
@@ -368,9 +367,9 @@
set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6);
/* LCLK Clock Gating */
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+ reg = pci_conf1_read_config32(PCI_BDF(0, 0, 1), 0x94);
reg &= ~(1 << 16);
- pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+ pci_conf1_write_config32(PCI_BDF(0, 0, 1), 0x94, reg);
}
if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) {
@@ -380,9 +379,9 @@
set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GPPSB, (3 << 6) | (~0xf), 3 << 6);
/* LCLK Clock Gating */
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+ reg = pci_conf1_read_config32(PCI_BDF(0, 0, 1),0x94);
reg &= ~(1 << 24);
- pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+ pci_conf1_write_config32(PCI_BDF(0, 0, 1), 0x94, reg);
}
reg = pci_read_config32(nb_dev, 0x4c);
@@ -419,4 +418,4 @@
.vendor = PCI_VENDOR_ID_ATI,
.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8,
};
-*/
\ No newline at end of file
+*/
Modified: coreboot-v3/southbridge/amd/rs690/rs690.c
===================================================================
--- coreboot-v3/southbridge/amd/rs690/rs690.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/rs690/rs690.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -37,8 +37,8 @@
if (!nb_dev)
return nb_dev;
- if ((nb_dev->vendor != PCI_VENDOR_ID_ATI)
- || (nb_dev->device != PCI_DEVICE_ID_ATI_RS690_HT)) {
+ if ((nb_dev->id.pci.vendor != PCI_VENDOR_ID_ATI)
+ || (nb_dev->id.pci.device != PCI_DEVICE_ID_ATI_RS690_HT)) {
u32 id;
id = pci_read_config32(nb_dev, PCI_VENDOR_ID);
if (id != (PCI_VENDOR_ID_ATI | (PCI_DEVICE_ID_ATI_RS690_HT << 16))) {
@@ -51,38 +51,38 @@
/*****************************************
* Compliant with CIM_33's ATINB_MiscClockCtrl
*****************************************/
-void static rs690_config_misc_clk(struct device * nb_dev)
+static void rs690_config_misc_clk(struct device * nb_dev)
{
u32 reg;
u16 word;
/* u8 byte; */
- struct bus pbus; /* fake bus for dev0 fun1 */
+ u32 dev0fun1 = PCI_BDF(0,0,1);
reg = pci_read_config32(nb_dev, 0x4c);
reg |= 1 << 0;
pci_write_config32(nb_dev, 0x4c, reg);
- word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
+ word = pci_conf1_read_config16(dev0fun1, 0xf8);
word &= 0xf00;
- pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
+ pci_conf1_write_config16(dev0fun1, 0xf8, word);
- word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8);
+ word = pci_conf1_read_config16(dev0fun1, 0xe8);
word &= ~((1 << 12) | (1 << 13) | (1 << 14));
word |= 1 << 13;
- pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word);
+ pci_conf1_write_config16(dev0fun1, 0xe8, word);
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+ reg = pci_conf1_read_config32(dev0fun1, 0x94);
reg &= ~((1 << 16) | (1 << 24) | (1 << 28));
- pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+ pci_conf1_write_config32(dev0fun1, 0x94, reg);
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
+ reg = pci_conf1_read_config32(dev0fun1, 0x8c);
reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25));
reg |= 1 << 13;
- pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
+ pci_conf1_write_config32(dev0fun1, 0x8c, reg);
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+ reg = pci_conf1_read_config32(dev0fun1, 0xcc);
reg |= 1 << 24;
- pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+ pci_conf1_write_config32(dev0fun1, 0xcc, reg);
reg = nbmc_read_index(nb_dev, 0x7a);
reg &= ~0x3f;
@@ -91,25 +91,25 @@
set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
nbmc_write_index(nb_dev, 0x7a, reg);
/* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+ reg = pci_conf1_read_config32(dev0fun1, 0xcc);
reg &= ~(1 << 23);
reg |= 1 << 24;
- pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+ pci_conf1_write_config32(dev0fun1, 0xcc, reg);
#if 0
/* Powerdown reference clock to graphics core PLL in northbridge only mode */
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
+ reg = pci_conf1_read_config32(dev0fun1, 0x8c);
reg |= 1 << 21;
- pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
+ pci_conf1_write_config32(dev0fun1, 0x8c, reg);
/* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+ reg = pci_conf1_read_config32(dev0fun1, 0xcc);
reg |= (1 << 23) | (1 << 24);
- pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+ pci_conf1_write_config32(dev0fun1, 0xcc, reg);
/* Powerdown clock to memory controller in northbridge only mode */
- byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4);
+ byte = pci_conf1_read_config32(dev0fun1, 0xe4);
byte |= 1 << 0;
- pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg);
+ pci_conf1_write_config32(dev0fun1, 0xe4, reg);
/* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */
/* TODO: */
@@ -138,7 +138,7 @@
***********************************************/
void rs690_enable(struct device * dev)
{
- struct device * nb_dev = 0, sb_dev = 0;
+ struct device * nb_dev = 0, *sb_dev = 0;
int index = -1;
u32 i;
u32 devfn;
@@ -152,7 +152,7 @@
/**********************************************************
* Work for bus0, internal GFX located on bus1 and will return after find_nb_dev.
**********************************************************/
- i = (dev->path.u.pci.devfn) & ~7;
+ i = (dev->path.pci.devfn) & ~7;
for (devfn = 0; devfn <= i; devfn += (1 << 3)) {
nb_dev = find_nb_dev(dev, devfn);
if (nb_dev)
@@ -170,8 +170,8 @@
for (;;) ;
}
- printk(BIOS_INFO, "rs690_enable bus0, dev=0x%x\n", (dev->path.u.pci.devfn - devfn) >> 3);
- switch (dev->path.u.pci.devfn - devfn) {
+ printk(BIOS_INFO, "rs690_enable bus0, dev=0x%x\n", (dev->path.pci.devfn - devfn) >> 3);
+ switch (dev->path.pci.devfn - devfn) {
case 0: /* bus0, dev0, fun0; */
printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n");
enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
@@ -190,7 +190,7 @@
case 2 << 3: /* bus0, dev2,3, two GFX */
case 3 << 3:
printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
- index = (dev->path.u.pci.devfn - devfn) >> 3;
+ index = (dev->path.pci.devfn - devfn) >> 3;
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << index,
(dev->enabled ? 0 : 1) << index);
if (dev->enabled)
@@ -202,7 +202,7 @@
case 7 << 3:
printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
dev->enabled);
- index = (dev->path.u.pci.devfn - devfn) >> 3;
+ index = (dev->path.pci.devfn - devfn) >> 3;
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << index,
(dev->enabled ? 0 : 1) << index);
if (dev->enabled)
@@ -220,20 +220,3 @@
printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
}
}
-
-struct chip_operations southbridge_amd_rs690_ops = {
- CHIP_NAME("ATI RS690")
- .enable_dev = rs690_enable,
-};
-struct device_operations rs690_sb = {
- .id = {.type = DEVICE_ID_PCI,
- {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
- .device = PCI_DEVICE_ID_NVIDIA_MCP55_IDE}}},
- .constructor = default_device_constructor,
- .phase3_scan = 0,
- .phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
- .phase5_enable_resources = pci_dev_enable_resources,
- .phase6_init = ide_init,
- .ops_pci = &pci_dev_ops_pci,
-};
Modified: coreboot-v3/southbridge/amd/rs690/rs690.h
===================================================================
--- coreboot-v3/southbridge/amd/rs690/rs690.h 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/rs690/rs690.h 2008-10-06 17:12:38 UTC (rev 893)
@@ -19,9 +19,8 @@
#ifndef __RS690_H__
#define __RS690_H__
+#include <types.h>
-#include <stdint.h>
-
#define PCI_DEVICE_ID_ATI_RS690_HT 0x7910
#define PCI_DEVICE_ID_ATI_RS690_PCIE 0x7912
#define PCI_DEVICE_ID_ATI_RS690_PCIE_DEV2 0x7913
@@ -115,37 +114,37 @@
extern PCIE_CFG AtiPcieCfg;
/* ----------------- export functions ----------------- */
-u32 nbmisc_read_index(device_t nb_dev, u32 index);
-void nbmisc_write_index(device_t nb_dev, u32 index, u32 data);
-u32 nbpcie_p_read_index(device_t dev, u32 index);
-void nbpcie_p_write_index(device_t dev, u32 index, u32 data);
-u32 nbpcie_ind_read_index(device_t nb_dev, u32 index);
-void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data);
-u32 htiu_read_index(device_t nb_dev, u32 index);
-void htiu_write_index(device_t nb_dev, u32 index, u32 data);
-u32 nbmc_read_index(device_t nb_dev, u32 index);
-void nbmc_write_index(device_t nb_dev, u32 index, u32 data);
+u32 nbmisc_read_index(struct device * nb_dev, u32 index);
+void nbmisc_write_index(struct device * nb_dev, u32 index, u32 data);
+u32 nbpcie_p_read_index(struct device * dev, u32 index);
+void nbpcie_p_write_index(struct device * dev, u32 index, u32 data);
+u32 nbpcie_ind_read_index(struct device * nb_dev, u32 index);
+void nbpcie_ind_write_index(struct device * nb_dev, u32 index, u32 data);
+u32 htiu_read_index(struct device * nb_dev, u32 index);
+void htiu_write_index(struct device * nb_dev, u32 index, u32 data);
+u32 nbmc_read_index(struct device * nb_dev, u32 index);
+void nbmc_write_index(struct device * nb_dev, u32 index, u32 data);
-u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg);
-void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val);
+u32 pci_ext_read_config32(struct device * nb_dev, struct device * dev, u32 reg);
+void pci_ext_write_config32(struct device * nb_dev, struct device * dev, u32 reg, u32 mask, u32 val);
-void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
-void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val);
-void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
-void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
-void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
-void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val);
-void rs690_set_tom(device_t nb_dev);
+void set_nbcfg_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val);
+void set_nbcfg_enable_bits_8(struct device * nb_dev, u32 reg_pos, u8 mask, u8 val);
+void set_nbmc_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val);
+void set_htiu_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val);
+void set_nbmisc_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val);
+void set_pcie_enable_bits(struct device * dev, u32 reg_pos, u32 mask, u32 val);
+void rs690_set_tom(struct device * nb_dev);
void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);
-void enable_pcie_bar3(device_t nb_dev);
-void disable_pcie_bar3(device_t nb_dev);
+void enable_pcie_bar3(struct device * nb_dev);
+void disable_pcie_bar3(struct device * nb_dev);
-void rs690_enable(device_t dev);
-void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port);
-void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port);
-void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev);
-void config_gpp_core(device_t nb_dev, device_t sb_dev);
-void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);
-u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);
+void rs690_enable(struct device * dev);
+void rs690_gpp_sb_init(struct device * nb_dev, struct device * dev, u32 port);
+void rs690_gfx_init(struct device * nb_dev, struct device * dev, u32 port);
+void avoid_lpc_dma_deadlock(struct device * nb_dev, struct device * sb_dev);
+void config_gpp_core(struct device * nb_dev, struct device * sb_dev);
+void PcieReleasePortTraining(struct device * nb_dev, struct device * dev, u32 port);
+u8 PcieTrainPort(struct device * nb_dev, struct device * dev, u32 port);
#endif /* RS690_H */
Modified: coreboot-v3/southbridge/amd/rs690/stage1.c
===================================================================
--- coreboot-v3/southbridge/amd/rs690/stage1.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/rs690/stage1.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -33,112 +33,112 @@
#define NBMISC_INDEX 0x60
#define NBMC_INDEX 0xE8
-static u32 nb_read_index(u32 dev, u32 index_reg, u32 index)
+static u32 nb_bdf_read_index(u32 bdf, u32 index_reg, u32 index)
{
- pci_conf1_write_config32(dev, index_reg, index);
- return pci_conf1_read_config32(dev, index_reg + 0x4);
+ pci_conf1_write_config32(bdf, index_reg, index);
+ return pci_conf1_read_config32(bdf, index_reg + 0x4);
}
-static void nb_write_index(u32 dev, u32 index_reg, u32 index, u32 data)
+static void nb_bdf_write_index(u32 bdf, u32 index_reg, u32 index, u32 data)
{
- pci_conf1_write_config32(dev, index_reg, index /* | 0x80 */ );
- pci_conf1_write_config32(dev, index_reg + 0x4, data);
+ pci_conf1_write_config32(bdf, index_reg, index /* | 0x80 */ );
+ pci_conf1_write_config32(bdf, index_reg + 0x4, data);
}
-static u32 nbmisc_read_index(u32 nb_dev, u32 index)
+static u32 nbmisc_bdf_read_index(u32 nb_bdf, u32 index)
{
- return nb_read_index((nb_dev), NBMISC_INDEX, (index));
+ return nb_bdf_read_index((nb_bdf), NBMISC_INDEX, (index));
}
-static void nbmisc_write_index(u32 nb_dev, u32 index, u32 data)
+static void nbmisc_bdf_write_index(u32 nb_bdf, u32 index, u32 data)
{
- nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
+ nb_bdf_write_index((nb_bdf), NBMISC_INDEX, ((index) | 0x80), (data));
}
-static u32 htiu_read_index(u32 nb_dev, u32 index)
+static u32 htiu_bdf_read_index(u32 nb_bdf, u32 index)
{
- return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
+ return nb_bdf_read_index((nb_bdf), NBHTIU_INDEX, (index));
}
-static void htiu_write_index(u32 nb_dev, u32 index, u32 data)
+static void htiu_bdf_write_index(u32 nb_bdf, u32 index, u32 data)
{
- nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
+ nb_bdf_write_index((nb_bdf), NBHTIU_INDEX, ((index) | 0x100), (data));
}
-static u32 nbmc_read_index(u32 nb_dev, u32 index)
+static u32 nbmc_bdf_read_index(u32 nb_bdf, u32 index)
{
- return nb_read_index((nb_dev), NBMC_INDEX, (index));
+ return nb_bdf_read_index((nb_bdf), NBMC_INDEX, (index));
}
-static void nbmc_write_index(u32 nb_dev, u32 index, u32 data)
+static void nbmc_bdf_write_index(u32 nb_bdf, u32 index, u32 data)
{
- nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
+ nb_bdf_write_index((nb_bdf), NBMC_INDEX, ((index) | 1 << 9), (data));
}
-static void set_htiu_enable_bits(u32 nb_dev, u32 reg_pos, u32 mask,
+static void set_htiu_bdf_enable_bits(u32 nb_bdf, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
- reg = reg_old = htiu_read_index(nb_dev, reg_pos);
+ reg = reg_old = htiu_bdf_read_index(nb_bdf, reg_pos);
reg &= ~mask;
reg |= val;
if (reg != reg_old) {
- htiu_write_index(nb_dev, reg_pos, reg);
+ htiu_bdf_write_index(nb_bdf, reg_pos, reg);
}
}
-static void set_nbmisc_enable_bits(u32 nb_dev, u32 reg_pos, u32 mask,
+static void set_nbmisc_bdf_enable_bits(u32 nb_bdf, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
- reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
+ reg = reg_old = nbmisc_bdf_read_index(nb_bdf, reg_pos);
reg &= ~mask;
reg |= val;
if (reg != reg_old) {
- nbmisc_write_index(nb_dev, reg_pos, reg);
+ nbmisc_bdf_write_index(nb_bdf, reg_pos, reg);
}
}
-static void set_nbcfg_enable_bits(u32 nb_dev, u32 reg_pos, u32 mask,
+static void set_nbcfg_bdf_enable_bits(u32 nb_bdf, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
- reg = reg_old = pci_conf1_read_config32(nb_dev, reg_pos);
+ reg = reg_old = pci_conf1_read_config32(nb_bdf, reg_pos);
reg &= ~mask;
reg |= val;
if (reg != reg_old) {
- pci_conf1_write_config32(nb_dev, reg_pos, reg);
+ pci_conf1_write_config32(nb_bdf, reg_pos, reg);
}
}
-static void set_nbcfg_enable_bits_8(u32 nb_dev, u32 reg_pos, u8 mask,
+static void set_nbcfg_bdf_enable_bits_8(u32 nb_bdf, u32 reg_pos, u8 mask,
u8 val)
{
u8 reg_old, reg;
- reg = reg_old = pci_conf1_read_config8(nb_dev, reg_pos);
+ reg = reg_old = pci_conf1_read_config8(nb_bdf, reg_pos);
reg &= ~mask;
reg |= val;
if (reg != reg_old) {
- pci_conf1_write_config8(nb_dev, reg_pos, reg);
+ pci_conf1_write_config8(nb_bdf, reg_pos, reg);
}
}
-static void set_nbmc_enable_bits(u32 nb_dev, u32 reg_pos, u32 mask,
+static void set_nbmc_bdf_enable_bits(u32 nb_bdf, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
- reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
+ reg = reg_old = nbmc_bdf_read_index(nb_bdf, reg_pos);
reg &= ~mask;
reg |= val;
if (reg != reg_old) {
- nbmc_write_index(nb_dev, reg_pos, reg);
+ nbmc_bdf_write_index(nb_bdf, reg_pos, reg);
}
}
/*
* Compliant with CIM_33's ATINB_PrepareInit
*/
-static void get_cpu_rev()
+static void get_cpu_rev(void)
{
u32 eax, ebx, ecx, edx;
__asm__ volatile ("cpuid":"=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
@@ -162,13 +162,13 @@
printk(BIOS_INFO, "CPU Rev is K8_10.\n");
}
-static u8 get_nb_rev(u32 nb_dev)
+static u8 get_nb_bdf_rev(u32 nb_bdf)
{
u32 reg;
- reg = pci_conf1_read_config32(nb_dev, 0x00);
+ reg = pci_conf1_read_config32(nb_bdf, 0x00);
if (0x7911 == (reg >> 16))
return 7;
- reg = pci_conf1_read_config8(nb_dev, 0x89); /* copy from CIM, can't find in doc */
+ reg = pci_conf1_read_config8(nb_bdf, 0x89); /* copy from CIM, can't find in doc */
if (reg & 0x2) /* check bit1 */
return 7;
if (reg & 0x1) /* check bit0 */
@@ -181,7 +181,7 @@
* Compliant with CIM_33's ATINB_HTInit
* Init HT link speed/width for rs690 -- k8 link
*****************************************/
-static void rs690_htinit()
+static void rs690_htinit(void)
{
/*
* About HT, it has been done in enumerate_ht_chain().
@@ -190,7 +190,7 @@
u32 reg;
u8 k8_ht_freq;
- k8_f0 = PCI_DEV(0, 0x18, 0);
+ k8_f0 = PCI_BDF(0, 0x18, 0);
/************************
* get k8's ht freq, in k8's function 0, offset 0x88
* bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
@@ -213,7 +213,7 @@
* Optimize k8 with UMA.
* See BKDG_NPT_0F guide for details.
* The processor node is addressed by its Node ID on the HT link and can be
-* accessed with a device number in the PCI configuration space on Bus0.
+* accessed with a bdfice number in the PCI configuration space on Bus0.
* The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped
* to Device 25, and so on.
* The processor implements configuration registers in PCI configuration
@@ -223,22 +223,22 @@
* Function2: DRAM and HT technology Trace mode configuration
* Function3: Miscellaneous configuration
*******************************************************/
-static void k8_optimization()
+static void k8_optimization(void)
{
u32 k8_f0, k8_f2, k8_f3;
- msr_t msr;
+ struct msr msr;
printk(BIOS_INFO, "k8_optimization()\n");
- k8_f0 = PCI_DEV(0, 0x18, 0);
- k8_f2 = PCI_DEV(0, 0x18, 2);
- k8_f3 = PCI_DEV(0, 0x18, 3);
+ k8_f0 = PCI_BDF(0, 0x18, 0);
+ k8_f2 = PCI_BDF(0, 0x18, 2);
+ k8_f3 = PCI_BDF(0, 0x18, 3);
pci_conf1_write_config32(k8_f0, 0x90, 0x01700178); /* CIM NPT_Optimization */
- set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28);
- set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 26 | 1 << 27,
+ set_nbcfg_bdf_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28);
+ set_nbcfg_bdf_enable_bits(k8_f0, 0x68, 1 << 26 | 1 << 27,
1 << 26 | 1 << 27);
- set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11);
- set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); /* TODO */
+ set_nbcfg_bdf_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11);
+ set_nbcfg_bdf_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); /* TODO */
pci_conf1_write_config32(k8_f3, 0x70, 0x51320111); /* CIM NPT_Optimization */
pci_conf1_write_config32(k8_f3, 0x74, 0x50304021);
@@ -247,13 +247,13 @@
pci_conf1_write_config32(k8_f3, 0x7C, 0x0000211B); /* dual core */
else
pci_conf1_write_config32(k8_f3, 0x7C, 0x0000211C); /* single core */
- set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25);
+ set_nbcfg_bdf_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25);
- set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
- set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24);
- set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 1 << 10);
- set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2);
- set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
+ set_nbcfg_bdf_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
+ set_nbcfg_bdf_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24);
+ set_nbcfg_bdf_enable_bits(k8_f2, 0x90, 1 << 10, 1 << 10);
+ set_nbcfg_bdf_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2);
+ set_nbcfg_bdf_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
msr = rdmsr(0xC001001F);
msr.lo &= ~(1 << 9);
@@ -264,80 +264,80 @@
/*****************************************
* Compliant with CIM_33's ATINB_PCICFG_POR_TABLE
*****************************************/
-static void rs690_por_pcicfg_init(u32 nb_dev)
+static void rs690_por_pcicfg_init(u32 nb_bdf)
{
/* enable PCI Memory Access */
- set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02);
+ set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x04, (u8)(~0xFD), 0x02);
/* Set RCRB Enable */
- set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x1);
+ set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x84, (u8)(~0xFF), 0x1);
/* allow decode of 640k-1MB */
- set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xEF), 0x10);
+ set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x84, (u8)(~0xEF), 0x10);
/* Enable PM2_CNTL(BAR2) IO mapped cfg write access to be broadcast to both NB and SB */
- set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x4);
+ set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x84, (u8)(~0xFF), 0x4);
/* Power Management Register Enable */
- set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x80);
+ set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x84, (u8)(~0xFF), 0x80);
/* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
* Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
* BMMsgEn */
- set_nbcfg_enable_bits_8(nb_dev, 0x4C, (u8)(~0x00), 0x42 | 1);
+ set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x4C, (u8)(~0x00), 0x42 | 1);
/* Reg4Ch[16]=1 (WakeC2En) enable Wake_from_C2 message generation.
* Reg4Ch[18]=1 (P4IntEnable) Enable north-bridge to accept MSI with address 0xFEEx_xxxx from south-bridge */
- set_nbcfg_enable_bits_8(nb_dev, 0x4E, (u8)(~0xFF), 0x05);
+ set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x4E, (u8)(~0xFF), 0x05);
/* Reg94h[4:0] = 0x0 P drive strength offset 0
* Reg94h[6:5] = 0x2 P drive strength additive adjust */
- set_nbcfg_enable_bits_8(nb_dev, 0x94, (u8)(~0x80), 0x40);
+ set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x94, (u8)(~0x80), 0x40);
/* Reg94h[20:16] = 0x0 N drive strength offset 0
* Reg94h[22:21] = 0x2 N drive strength additive adjust */
- set_nbcfg_enable_bits_8(nb_dev, 0x96, (u8)(~0x80), 0x40);
+ set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x96, (u8)(~0x80), 0x40);
/* Reg80h[4:0] = 0x0 Termination offset
* Reg80h[6:5] = 0x2 Termination additive adjust */
- set_nbcfg_enable_bits_8(nb_dev, 0x80, (u8)(~0x80), 0x40);
+ set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x80, (u8)(~0x80), 0x40);
/* Reg80h[14] = 0x1 Enable receiver termination control */
- set_nbcfg_enable_bits_8(nb_dev, 0x81, (u8)(~0xFF), 0x40);
+ set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x81, (u8)(~0xFF), 0x40);
/* Reg94h[15] = 0x1 Enables HT transmitter advanced features to be turned on
* Reg94h[14] = 0x1 Enable drive strength control */
- set_nbcfg_enable_bits_8(nb_dev, 0x95, (u8)(~0x3F), 0xC4);
+ set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x95, (u8)(~0x3F), 0xC4);
/* Reg94h[31:29] = 0x7 Enables HT transmitter de-emphasis */
- set_nbcfg_enable_bits_8(nb_dev, 0x97, (u8)(~0x1F), 0xE0);
+ set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x97, (u8)(~0x1F), 0xE0);
/*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
* force this BAR as mem type in rs690_gfx.c */
- set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03);
+ set_nbcfg_bdf_enable_bits_8(nb_bdf, 0x8D, (u8)(~0xFF), 0x03);
}
/*****************************************
* Compliant with CIM_33's ATINB_MCIndex_POR_TABLE
*****************************************/
-static void rs690_por_mc_index_init(u32 nb_dev)
+static void rs690_por_mc_index_init(u32 nb_bdf)
{
- set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F);
- set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060);
- set_nbmc_enable_bits(nb_dev, 0xD9, ~0x00000000, 0x00600060);
- set_nbmc_enable_bits(nb_dev, 0xE0, ~0x00000000, 0x00000000);
- set_nbmc_enable_bits(nb_dev, 0xE1, ~0x00000000, 0x00000000);
- set_nbmc_enable_bits(nb_dev, 0xE8, ~0x00000000, 0x003E003E);
- set_nbmc_enable_bits(nb_dev, 0xE9, ~0x00000000, 0x003E003E);
+ set_nbmc_bdf_enable_bits(nb_bdf, 0x7A, ~0xFFFFFF80, 0x0000005F);
+ set_nbmc_bdf_enable_bits(nb_bdf, 0xD8, ~0x00000000, 0x00600060);
+ set_nbmc_bdf_enable_bits(nb_bdf, 0xD9, ~0x00000000, 0x00600060);
+ set_nbmc_bdf_enable_bits(nb_bdf, 0xE0, ~0x00000000, 0x00000000);
+ set_nbmc_bdf_enable_bits(nb_bdf, 0xE1, ~0x00000000, 0x00000000);
+ set_nbmc_bdf_enable_bits(nb_bdf, 0xE8, ~0x00000000, 0x003E003E);
+ set_nbmc_bdf_enable_bits(nb_bdf, 0xE9, ~0x00000000, 0x003E003E);
}
/*****************************************
* Compliant with CIM_33's ATINB_MISCIND_POR_TABLE
* Compliant with CIM_33's MISC_INIT_TBL
*****************************************/
-static void rs690_por_misc_index_init(u32 nb_dev)
+static void rs690_por_misc_index_init(u32 nb_bdf)
{
/* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL
* Block non-snoop DMA request if PMArbDis is set.
* Set BMSetDis */
- set_nbmisc_enable_bits(nb_dev, 0x0B, ~0xFFFF0000, 0x00000180);
- set_nbmisc_enable_bits(nb_dev, 0x01, ~0xFFFFFFFF, 0x00000040);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x0B, ~0xFFFF0000, 0x00000180);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x01, ~0xFFFFFFFF, 0x00000040);
/* NBCFG (NBMISCIND 0x0): NB_CNTL -
* HIDE_NB_AGP_CAP ([0], default=1)HIDE
@@ -346,51 +346,51 @@
* AGPMODE30 ([4], default=0)DISABLE
* AGP30ENCHANCED ([5], default=0)DISABLE
* HIDE_AGP_CAP ([8], default=1)ENABLE */
- set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000506); /* set bit 10 for MSI */
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x00, ~0xFFFF0000, 0x00000506); /* set bit 10 for MSI */
/* NBMISCIND:0x6A[16]= 1 SB link can get a full swing
- * set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000);
+ * set_nbmisc_bdf_enable_bits(nb_bdf, 0x6A, 0ffffffffh, 000010000);
* NBMISCIND:0x6A[17]=1 Set CMGOOD_OVERRIDE. */
- set_nbmisc_enable_bits(nb_dev, 0x6A, ~0xffffffff, 0x00020000);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x6A, ~0xffffffff, 0x00020000);
/* NBMISIND:0x40 Bit[8]=1 and Bit[10]=1 following bits are required to set in order to allow LVDS or PWM features to work. */
- set_nbmisc_enable_bits(nb_dev, 0x40, ~0xffffffff, 0x00000500);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x40, ~0xffffffff, 0x00000500);
/* NBMISIND:0xC Bit[13]=1 Enable GSM mode for C1e or C3 with pop-up. */
- set_nbmisc_enable_bits(nb_dev, 0x0C, ~0xffffffff, 0x00002000);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x0C, ~0xffffffff, 0x00002000);
/* Set NBMISIND:0x1F[3] to map NB F2 interrupt pin to INTB# */
- set_nbmisc_enable_bits(nb_dev, 0x1F, ~0xffffffff, 0x00000008);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x1F, ~0xffffffff, 0x00000008);
/* Compliant with CIM_33's MISC_INIT_TBL, except Hide NB_BAR3_PCIE
* Enable access to DEV8
* Enable setPower message for all ports
*/
- set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, 1 << 6);
- set_nbmisc_enable_bits(nb_dev, 0x0b, 1 << 20, 1 << 20);
- set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20, 1 << 20);
- set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20, 1 << 20);
- set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20, 1 << 20);
- set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20, 1 << 20);
- set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20, 1 << 20);
- set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20, 1 << 20);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x00, 1 << 6, 1 << 6);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x0b, 1 << 20, 1 << 20);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x51, 1 << 20, 1 << 20);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x53, 1 << 20, 1 << 20);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x55, 1 << 20, 1 << 20);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x57, 1 << 20, 1 << 20);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x59, 1 << 20, 1 << 20);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x5B, 1 << 20, 1 << 20);
- set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7);
- set_nbmisc_enable_bits(nb_dev, 0x07, 0x000000f0, 0x30);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x00, 1 << 7, 1 << 7);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x07, 0x000000f0, 0x30);
/* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */
- set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x500180);
+ set_nbmisc_bdf_enable_bits(nb_bdf, 0x0B, 0xffffffff, 0x500180);
}
/*****************************************
* Compliant with CIM_33's ATINB_HTIUNBIND_POR_TABLE
*****************************************/
-static void rs690_por_htiu_index_init(u32 nb_dev)
+static void rs690_por_htiu_index_init(u32 nb_bdf)
{
/* 0xBC:
* Enables GSM mode for C1e or C3 with pop-up
* Prevents AllowLdtStop from being asserted during HT link recovery
* Allows FID cycles to be serviced faster. Needed for RS690 A12. No harm in RS690 A11 */
- set_htiu_enable_bits(nb_dev, 0x05, ~0xffffffff, 0x0BC);
+ set_htiu_bdf_enable_bits(nb_bdf, 0x05, ~0xffffffff, 0x0BC);
/* 0x4203A202:
* Enables writes to pass in-progress reads
* Enables streaming of CPU writes
@@ -400,15 +400,15 @@
* Enables decoding of C1e/C3 and FID cycles
* Enables HTIU-display handshake bypass.
* Enables tagging fix */
- set_htiu_enable_bits(nb_dev, 0x06, ~0xFFFFFFFE, 0x4203A202);
+ set_htiu_bdf_enable_bits(nb_bdf, 0x06, ~0xFFFFFFFE, 0x4203A202);
/* Enables byte-write optimization for IOC requests
* Disables delaying STPCLK de-assert during FID sequence. Needed when enhanced UMA arbitration is used.
* Disables upstream system-management delay */
- set_htiu_enable_bits(nb_dev, 0x07, ~0xFFFFFFF9, 0x001);
+ set_htiu_bdf_enable_bits(nb_bdf, 0x07, ~0xFFFFFFF9, 0x001);
/* HTIUNBIND 0x16 [1] = 0x1 Enable crc decoding fix */
- set_htiu_enable_bits(nb_dev, 0x16, ~0xFFFFFFFF, 0x2);
+ set_htiu_bdf_enable_bits(nb_bdf, 0x16, ~0xFFFFFFFF, 0x2);
}
/*****************************************
@@ -417,29 +417,29 @@
* POR: Power On Reset
* RPR: Register Programming Requirements
*****************************************/
-static void rs690_por_init(u32 nb_dev)
+static void rs690_por_init(u32 nb_bdf)
{
printk(BIOS_INFO, "rs690_por_init\n");
/* ATINB_PCICFG_POR_TABLE, initialize the values for rs690 PCI Config registers */
- rs690_por_pcicfg_init(nb_dev);
+ rs690_por_pcicfg_init(nb_bdf);
/* ATINB_MCIND_POR_TABLE */
- rs690_por_mc_index_init(nb_dev);
+ rs690_por_mc_index_init(nb_bdf);
/* ATINB_MISCIND_POR_TABLE */
- rs690_por_misc_index_init(nb_dev);
+ rs690_por_misc_index_init(nb_bdf);
/* ATINB_HTIUNBIND_POR_TABLE */
- rs690_por_htiu_index_init(nb_dev);
+ rs690_por_htiu_index_init(nb_bdf);
/* ATINB_CLKCFG_PORT_TABLE */
/* rs690 A11 SB Link full swing? */
}
/* enable CFG access to Dev8, which is the SB P2P Bridge */
-static void enable_rs690_dev8()
+void enable_rs690_dev8(void)
{
- set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
+ set_nbmisc_bdf_enable_bits(PCI_BDF(0, 0, 0), 0x00, 1 << 6, 1 << 6);
}
@@ -447,21 +447,21 @@
/*
* Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit).
*/
-void rs690_before_pci_init()
+void rs690_before_pci_init(void)
{
}
/*
* The calling sequence is same as CIM.
*/
-void rs690_early_setup()
+void rs690_stage1(void)
{
- u32 nb_dev = PCI_DEV(0, 0, 0);
+ u32 nb_bdf = PCI_BDF(0, 0, 0);
printk(BIOS_INFO, "rs690_early_setup()\n");
/*ATINB_PrepareInit */
get_cpu_rev();
- switch (get_nb_rev(nb_dev)) { /* PCIEMiscInit */
+ switch (get_nb_bdf_rev(nb_bdf)) { /* PCIEMiscInit */
case 5:
printk(BIOS_INFO, "NB Revision is A11.\n");
break;
@@ -475,5 +475,5 @@
rs690_htinit();
k8_optimization();
- rs690_por_init(nb_dev);
+ rs690_por_init(nb_bdf);
}
Added: coreboot-v3/southbridge/amd/sb600/Makefile
===================================================================
--- coreboot-v3/southbridge/amd/sb600/Makefile (rev 0)
+++ coreboot-v3/southbridge/amd/sb600/Makefile 2008-10-06 17:12:38 UTC (rev 893)
@@ -0,0 +1,40 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 coresystems GmbH
+## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB600),y)
+
+STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/sb600/sb600.c
+
+STAGE2_CHIPSET_SRC += \
+ $(src)/southbridge/amd/sb600/ac97.c \
+ $(src)/southbridge/amd/sb600/hda.c \
+ $(src)/southbridge/amd/sb600/ide.c \
+ $(src)/southbridge/amd/sb600/lpc.c \
+ $(src)/southbridge/amd/sb600/pci.c \
+ $(src)/southbridge/amd/sb600/sata.c \
+ $(src)/southbridge/amd/sb600/sm.c \
+ $(src)/southbridge/amd/sb600/usb.c
+
+STAGE0_CHIPSET_SRC += $(src)/southbridge/amd/sb600/stage1.c \
+ $(src)/southbridge/amd/sb600/stage1_reset.c \
+ $(src)/southbridge/amd/sb600/stage1_smbus.c
+
+endif
Modified: coreboot-v3/southbridge/amd/sb600/hda.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/hda.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/sb600/hda.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -24,6 +24,7 @@
#include <msr.h>
#include <legacy.h>
#include <device/pci_ids.h>
+#include <io.h>
#include <statictree.h>
#include <config.h>
#include "sb600.h"
@@ -149,8 +150,7 @@
static unsigned find_verb(u32 viddid, u32 ** verb)
{
struct device * azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));
- struct southbridge_amd_sb600_dts_config *cfg =
- (struct southbridge_amd_sb600_config *)azalia_dev->chip_info;
+ struct southbridge_amd_sb600_hda_config *cfg = azalia_dev->device_configuration;
printk(BIOS_DEBUG, "Dev=%s\n", dev_path(azalia_dev));
printk(BIOS_DEBUG, "Default viddid=%x\n", cfg->hda_viddid);
printk(BIOS_DEBUG, "Reading viddid=%x\n", viddid);
@@ -239,7 +239,7 @@
return;
base = (u8 *) ((u32)res->base);
- printk(BIOS_DEBUG, "base = %08x\n", base);
+ printk(BIOS_DEBUG, "base = %p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
Modified: coreboot-v3/southbridge/amd/sb600/hda.dts
===================================================================
--- coreboot-v3/southbridge/amd/sb600/hda.dts 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/sb600/hda.dts 2008-10-06 17:12:38 UTC (rev 893)
@@ -20,4 +20,5 @@
{
device_operations = "sb600_hda";
+ hda_viddid = "0";
};
Modified: coreboot-v3/southbridge/amd/sb600/ide.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/ide.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/sb600/ide.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -55,7 +55,7 @@
dword |= 1 << 2;
pci_write_config16(dev, 0x4, dword);
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_OPTION_ROM_RUN == 1
pci_dev_init(dev);
#endif
Modified: coreboot-v3/southbridge/amd/sb600/lpc.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/lpc.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/sb600/lpc.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -109,7 +109,7 @@
struct device * child;
for (child = dev->link[link].children; child;
child = child->sibling) {
- enable_resources(child);
+ dev_phase5(child);
if (child->have_resources
&& (child->path.type == DEVICE_PATH_PNP)) {
for (i = 0; i < child->resources; i++) {
@@ -120,8 +120,7 @@
continue;
base = res->base;
end = resource_end(res);
- printk_debug
- ("sb600 lpc decode:%s, base=0x%08x, end=0x%08x\n",
+ printk(BIOS_DEBUG, "sb600 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",
dev_path(child), base, end);
switch (base) {
case 0x60: /* KB */
@@ -213,7 +212,7 @@
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB600_LPC}}},
.constructor = default_device_constructor,
- .phase3_scan_bus = scan_status_bus,
+ .phase3_scan = scan_static_bus,
.phase4_read_resources = sb600_lpc_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = sb600_lpc_enable_resources,
Modified: coreboot-v3/southbridge/amd/sb600/pci.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/pci.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/sb600/pci.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -17,11 +17,15 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <console/console.h>
-#include <device/device.h>
+#include <types.h>
+#include <lib.h>
+#include <console.h>
#include <device/pci.h>
+#include <msr.h>
+#include <legacy.h>
#include <device/pci_ids.h>
-#include <device/pci_ops.h>
+#include <statictree.h>
+#include <config.h>
#include "sb600.h"
static void pci_init(struct device *dev)
Modified: coreboot-v3/southbridge/amd/sb600/sata.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/sata.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/sb600/sata.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -24,6 +24,7 @@
#include <msr.h>
#include <legacy.h>
#include <device/pci_ids.h>
+#include <io.h>
#include <statictree.h>
#include <config.h>
#include "sb600.h"
@@ -69,7 +70,7 @@
printk(BIOS_DEBUG, "sata_bar2=%x\n", sata_bar2); /* 3040 */
printk(BIOS_DEBUG, "sata_bar3=%x\n", sata_bar3); /* 3080 */
printk(BIOS_DEBUG, "sata_bar4=%x\n", sata_bar4); /* 3000 */
- printk(BIOS_DEBUG, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
+ printk(BIOS_DEBUG, "sata_bar5=%p\n", sata_bar5); /* e0309000 */
/* Program the 2C to 0x43801002 */
dword = 0x43801002;
@@ -197,4 +198,4 @@
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sata_init,
.ops_pci = &lops_pci
-};
\ No newline at end of file
+};
Modified: coreboot-v3/southbridge/amd/sb600/sb600.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/sb600.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/sb600/sb600.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -24,6 +24,7 @@
#include <msr.h>
#include <legacy.h>
#include <device/pci_ids.h>
+#include <io.h>
#include <statictree.h>
#include <config.h>
#include "sb600.h"
@@ -36,8 +37,8 @@
if (!sm_dev)
return sm_dev;
- if ((sm_dev->vendor != PCI_VENDOR_ID_ATI) ||
- ((sm_dev->device != PCI_DEVICE_ID_ATI_SB600_SM))) {
+ if ((sm_dev->id.pci.vendor != PCI_VENDOR_ID_ATI) ||
+ ((sm_dev->id.pci.device != PCI_DEVICE_ID_ATI_SB600_SM))) {
u32 id;
id = pci_read_config32(sm_dev, PCI_VENDOR_ID);
if ((id !=
@@ -61,42 +62,13 @@
}
}
-static void pmio_write_index(unsigned long port_base, u8 reg, u8 value)
-{
- outb(reg, port_base);
- outb(value, port_base + 1);
-}
+void pmio_write_index(unsigned long port_base, u8 reg, u8 value);
+u8 pmio_read_index(unsigned long port_base, u8 reg);
+u8 pm_ioread(u8 reg);
+void pm_iowrite(u8 reg, u8 value);
+void pm2_iowrite(u8 reg, u8 value);
+u8 pm2_ioread(u8 reg);
-static u8 pmio_read_index(unsigned long port_base, u8 reg)
-{
- outb(reg, port_base);
- return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
- unsigned long port_base = 0xcd6;
- pmio_write_index(port_base, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
- unsigned long port_base = 0xcd6;
- return pmio_read_index(port_base, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
- unsigned long port_base = 0xcd0;
- pmio_write_index(port_base, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
- unsigned long port_base = 0xcd0;
- return pmio_read_index(port_base, reg);
-}
-
static void set_pmio_enable_bits(struct device * sm_dev, u32 reg_pos,
u32 mask, u32 val)
{
@@ -140,17 +112,17 @@
* 0:14.5 ACI bit 0 of pm_io 0x59 : 0 - enable, default
* 0:14.6 MCI bit 1 of pm_io 0x59 : 0 - enable, default
*/
- if (dev->device == 0x0000) {
+ if (dev->id.pci.device == 0x0000) {
vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
deviceid = (vendorid >> 16) & 0xffff;
vendorid &= 0xffff;
} else {
- vendorid = dev->vendor;
- deviceid = dev->device;
+ vendorid = dev->id.pci.vendor;
+ deviceid = dev->id.pci.device;
}
bus_dev = dev->bus->dev;
- if ((bus_dev->vendor == PCI_VENDOR_ID_ATI) &&
- (bus_dev->device == PCI_DEVICE_ID_ATI_SB600_PCI)) {
+ if ((bus_dev->id.pci.vendor == PCI_VENDOR_ID_ATI) &&
+ (bus_dev->id.pci.device == PCI_DEVICE_ID_ATI_SB600_PCI)) {
devfn = (bus_dev->path.pci.devfn) & ~7;
sm_dev = find_sm_dev(bus_dev, devfn);
if (!sm_dev)
@@ -233,7 +205,7 @@
struct device_operations sb600 = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
- .device = xz}}},
+ .device = PCI_DEVICE_ID_ATI_SB600_LPC}}},
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_enable_disable = sb600_enable,
Modified: coreboot-v3/southbridge/amd/sb600/sb600.h
===================================================================
--- coreboot-v3/southbridge/amd/sb600/sb600.h 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/sb600/sb600.h 2008-10-06 17:12:38 UTC (rev 893)
@@ -35,12 +35,12 @@
#define PCI_DEVICE_ID_ATI_SB600_USB_3 0x438A
#define PCI_DEVICE_ID_ATI_SB600_USB_4 0x438B
-extern void pm_iowrite(u8 reg, u8 value);
-extern u8 pm_ioread(u8 reg);
-extern void pm2_iowrite(u8 reg, u8 value);
-extern u8 pm2_ioread(u8 reg);
-extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
+void pm_iowrite(u8 reg, u8 value);
+u8 pm_ioread(u8 reg);
+void pm2_iowrite(u8 reg, u8 value);
+u8 pm2_ioread(u8 reg);
+void set_sm_enable_bits(struct device * sm_dev, u32 reg_pos, u32 mask, u32 val);
-void sb600_enable(device_t dev);
+void sb600_enable(struct device * dev);
#endif /* SB600_H */
Modified: coreboot-v3/southbridge/amd/sb600/sb600_smbus.h
===================================================================
--- coreboot-v3/southbridge/amd/sb600/sb600_smbus.h 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/sb600/sb600_smbus.h 2008-10-06 17:12:38 UTC (rev 893)
@@ -58,5 +58,7 @@
#define axindxp_reg(reg, mask, val) \
alink_ax_indx(1, (reg), (mask), (val))
+#define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */
+ /*SIZE 0x40 */
#endif
Modified: coreboot-v3/southbridge/amd/sb600/sm.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/sm.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/sb600/sm.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -23,10 +23,15 @@
#include <msr.h>
#include <legacy.h>
#include <device/pci_ids.h>
+#include <device/smbus.h>
+#include <cpu.h>
+#include <lapic.h>
+#include <io.h>
#include <statictree.h>
#include <config.h>
+#include <mc146818rtc.h>
#include "sb600.h"
-#include "sb600_smbus.c"
+#include "sb600_smbus.h"
#define NMI_OFF 0
@@ -86,6 +91,18 @@
/* Be careful and don't write past the end... */
};
+void alink_ab_indx(unsigned int reg_space, unsigned int reg_addr,
+ unsigned int mask, unsigned int val);
+void alink_ax_indx(unsigned int space /*c or p? */ , unsigned int axindc,
+ unsigned int mask, unsigned int val);
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
+int do_smbus_read_byte(u32 smbus_io_base, u32 device,
+ u32 address);
+int do_smbus_write_byte(u32 smbus_io_base, u32 device,
+ u32 address, u8 val);
+int do_smbus_send_byte(u32 smbus_io_base, u32 device,
+ u8 val);
+
static void setup_ioapic(unsigned long ioapic_base)
{
int i;
@@ -108,7 +125,7 @@
l[4] = a->value_high;
value_high = l[4];
if ((i == 0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
+ printk(BIOS_WARNING, "IO APIC not responding.\n");
return;
}
}
@@ -382,6 +399,6 @@
.phase4_set_resources = sb600_sm_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sm_init,
- .ops_pci = &lops_pci
+ .ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
-};
\ No newline at end of file
+};
Modified: coreboot-v3/southbridge/amd/sb600/stage1.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/stage1.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/sb600/stage1.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -26,17 +26,49 @@
#include <statictree.h>
#include <config.h>
#include <io.h>
-BORKED
-#define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */
- /*SIZE 0x40 */
+#include <cpu.h>
+#include "sb600_smbus.h"
-/* Get SB ASIC Revision.*/
-static u8 get_sb600_revision()
+
+void pmio_write_index(unsigned long port_base, u8 reg, u8 value)
{
+ outb(reg, port_base);
+ outb(value, port_base + 1);
+}
+
+u8 pmio_read_index(unsigned long port_base, u8 reg)
+{
+ outb(reg, port_base);
+ return inb(port_base + 1);
+}
+
+void pm_iowrite(u8 reg, u8 value)
+{
+ unsigned long port_base = 0xcd6;
+ pmio_write_index(port_base, reg, value);
+}
+
+u8 pm_ioread(u8 reg)
+{
+ unsigned long port_base = 0xcd6;
+ return pmio_read_index(port_base, reg);
+}
+
+void pm2_iowrite(u8 reg, u8 value)
+{
+ unsigned long port_base = 0xcd0;
+ pmio_write_index(port_base, reg, value);
+}
+
+u8 pm2_ioread(u8 reg)
+{
+ unsigned long port_base = 0xcd0;
+ return pmio_read_index(port_base, reg);
+}/* Get SB ASIC Revision.*/
+static u8 get_sb600_revision(void)
+{
u32 dev;
- pci_conf1_find_device(0x1002, 0x4385, &dev);
-
- if (dev == PCI_DEV_INVALID) {
+ if (!pci_conf1_find_device(0x1002, 0x4385, &dev)){
die("SMBUS controller not found\r\n");
}
return pci_conf1_read_config8(dev, 0x08);
@@ -51,7 +83,7 @@
* LPC ROM size,
* NOTE: Call me ASAP, because I will reset LPC ROM size!
***************************************/
-static void sb600_lpc_init(void)
+void sb600_lpc_init(void)
{
u8 reg8;
u32 reg32;
@@ -89,7 +121,7 @@
}
/* what is its usage? */
-static u32 get_sbdn(u32 bus)
+u32 get_sbdn(u32 bus)
{
u32 dev;
@@ -99,7 +131,7 @@
}
-static u8 dual_core()
+u8 dual_core(void)
{
if(((cpuid_eax(0x80000000) & ~0xff) >= 8)) {
if(cpuid_ecx(0x80000008) & 1)
@@ -112,80 +144,72 @@
SB600 VFSMAF (VID/FID System Management Action Field) is 010b by default.
RPR 2.3.3 C-state and VID/FID change for the K8 platform.
*/
-static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
+void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
{
u8 byte;
- byte = pmio_read(0x9a);
+ byte = pm_ioread(0x9a);
byte &= ~0x34;
if(dual_core())
byte |= 0x34;
else
byte |= 0x04;
- pmio_write(0x9a, byte);
+ pm_iowrite(0x9a, byte);
- byte = pmio_read(0x8f);
+ byte = pm_ioread(0x8f);
byte &= ~0x30;
byte |= 0x20;
- pmio_write(0x8f, byte);
+ pm_iowrite(0x8f, byte);
- pmio_write(0x8b, 0x01);
- pmio_write(0x8a, 0x90);
+ pm_iowrite(0x8b, 0x01);
+ pm_iowrite(0x8a, 0x90);
if(get_sb600_revision() > 0x13)
- pmio_write(0x88, 0x10);
+ pm_iowrite(0x88, 0x10);
else
- pmio_write(0x88, 0x06);
+ pm_iowrite(0x88, 0x06);
- byte = pmio_read(0x7c);
+ byte = pm_ioread(0x7c);
byte &= ~0x01;
byte |= 0x01;
- pmio_write(0x7c, byte);
+ pm_iowrite(0x7c, byte);
/*Must be 0 for K8 platform.*/
- byte = pmio_read(0x68);
+ byte = pm_ioread(0x68);
byte &= ~0x01;
- pmio_write(0x68, byte);
+ pm_iowrite(0x68, byte);
/*Must be 0 for K8 platform.*/
- byte = pmio_read(0x8d);
+ byte = pm_ioread(0x8d);
byte &= ~(1<<6);
- pmio_write(0x8d, byte);
+ pm_iowrite(0x8d, byte);
- byte = pmio_read(0x61);
+ byte = pm_ioread(0x61);
byte &= ~0x04;
- pmio_write(0x61, byte);
+ pm_iowrite(0x61, byte);
- byte = pmio_read(0x42);
+ byte = pm_ioread(0x42);
byte &= ~0x04;
- pmio_write(0x42, byte);
+ pm_iowrite(0x42, byte);
if(get_sb600_revision() == 0x14) {
- pmio_write(0x89, 0x10);
+ pm_iowrite(0x89, 0x10);
- byte = pmio_read(0x52);
+ byte = pm_ioread(0x52);
byte |= 0x80;
- pmio_write(0x52, byte);
+ pm_iowrite(0x52, byte);
}
}
+void set_bios_reset(void);
-static void hard_reset(void)
+void soft_reset(void)
{
set_bios_reset();
-
- /* full reset */
- outb(0x0a, 0x0cf9);
- outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
- set_bios_reset();
/* link reset */
outb(0x06, 0x0cf9);
}
-static void sb600_pci_port80()
+void sb600_pci_port80(void)
{
u8 byte;
u32 dev;
@@ -220,7 +244,7 @@
pci_conf1_write_config8(dev, 0x4A, byte);
}
-static void sb600_lpc_port80(void)
+void sb600_lpc_port80(void)
{
u8 byte;
u32 dev;
@@ -241,17 +265,19 @@
/* sbDevicesPorInitTable */
-static void sb600_devices_por_init()
+static void sb600_devices_por_init(void)
{
+ void alink_ab_indx(unsigned int reg_space, unsigned int reg_addr,
+ unsigned int mask, unsigned int val);
+ void alink_ax_indx(unsigned int space /*c or p? */ , unsigned int axindc,
+ unsigned int mask, unsigned int val);
u32 dev;
u8 byte;
printk(BIOS_INFO, "sb600_devices_por_init()\n");
/* SMBus Device, BDF:0-20-0 */
printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n");
- pci_conf1_find_device(0x1002, 0x4385, &dev);
-
- if (dev == PCI_DEV_INVALID) {
+ if (!pci_conf1_find_device(0x1002, 0x4385, &dev)){
die("SMBUS controller not found\r\n");
}
printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\r\n",
@@ -436,94 +462,94 @@
* The index address is first programmed into IO reg 0xcd6.
* Read or write values are accessed through IO reg 0xcd7.
*/
-static void sb600_pmio_por_init()
+static void sb600_pmio_por_init(void)
{
u8 byte;
printk(BIOS_INFO, "sb600_pmio_por_init()\n");
/* K8KbRstEn, KB_RST# control for K8 system. */
- byte = pmio_read(0x66);
+ byte = pm_ioread(0x66);
byte |= 0x20;
- pmio_write(0x66, byte);
+ pm_iowrite(0x66, byte);
/* RPR2.3.4 S3/S4/S5 Function for the K8 Platform. */
- byte = pmio_read(0x52);
+ byte = pm_ioread(0x52);
byte &= 0xc0;
byte |= 0x08;
- pmio_write(0x52, byte);
+ pm_iowrite(0x52, byte);
/* C state enable and SLP enable in C states. */
- byte = pmio_read(0x67);
+ byte = pm_ioread(0x67);
byte |= 0x6;
- pmio_write(0x67, byte);
+ pm_iowrite(0x67, byte);
/* CIM sets 0x0e, but bit2 is for P4 system. */
- byte = pmio_read(0x68);
+ byte = pm_ioread(0x68);
byte &= 0xf0;
byte |= 0x0c;
- pmio_write(0x68, byte);
+ pm_iowrite(0x68, byte);
/* Watch Dog Timer Control
* Set watchdog time base to 0xfec000f0 to avoid SCSI card boot failure.
* But I don't find WDT is enabled in SMBUS 0x41 bit3 in CIM.
*/
- pmio_write(0x6c, 0xf0);
- pmio_write(0x6d, 0x00);
- pmio_write(0x6e, 0xc0);
- pmio_write(0x6f, 0xfe);
+ pm_iowrite(0x6c, 0xf0);
+ pm_iowrite(0x6d, 0x00);
+ pm_iowrite(0x6e, 0xc0);
+ pm_iowrite(0x6f, 0xfe);
/* rpr2.14: Enables HPET periodical mode */
- byte = pmio_read(0x9a);
+ byte = pm_ioread(0x9a);
byte |= 1 << 7;
- pmio_write(0x9a, byte);
- byte = pmio_read(0x9f);
+ pm_iowrite(0x9a, byte);
+ byte = pm_ioread(0x9f);
byte |= 1 << 5;
- pmio_write(0x9f, byte);
- byte = pmio_read(0x9e);
+ pm_iowrite(0x9f, byte);
+ byte = pm_ioread(0x9e);
byte |= (1 << 6) | (1 << 7);
- pmio_write(0x9e, byte);
+ pm_iowrite(0x9e, byte);
/* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */
- byte = pmio_read(0x55);
+ byte = pm_ioread(0x55);
byte |= 1 << 7;
- pmio_write(0x55, byte);
+ pm_iowrite(0x55, byte);
/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */
- byte = pmio_read(0x52);
+ byte = pm_ioread(0x52);
byte |= 1 << 6;
- pmio_write(0x52, byte);
+ pm_iowrite(0x52, byte);
/* rpr2.22: PLL Reset */
- byte = pmio_read(0x86);
+ byte = pm_ioread(0x86);
byte |= 1 << 7;
- pmio_write(0x86, byte);
+ pm_iowrite(0x86, byte);
/* rpr2.3.3 */
/* This provides 16us delay before the assertion of LDTSTP# when C3 is entered.
* The delay will allow USB DMA to go on in a continuous manner
*/
- pmio_write(0x89, 0x10);
+ pm_iowrite(0x89, 0x10);
/* Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time */
- byte = pmio_read(0x52);
+ byte = pm_ioread(0x52);
byte |= 1 << 7;
- pmio_write(0x52, byte);
+ pm_iowrite(0x52, byte);
/* rpr2.15: ASF Remote Control Action */
- byte = pmio_read(0x9f);
+ byte = pm_ioread(0x9f);
byte |= 1 << 6;
- pmio_write(0x9f, byte);
+ pm_iowrite(0x9f, byte);
/* rpr2.19: Enabling Spread Spectrum */
- byte = pmio_read(0x42);
+ byte = pm_ioread(0x42);
byte |= 1 << 7;
- pmio_write(0x42, byte);
+ pm_iowrite(0x42, byte);
}
/*
* Compliant with CIM_48's sbPciCfg.
* Add any south bridge setting.
*/
-static void sb600_pci_cfg()
+static void sb600_pci_cfg(void)
{
u32 dev;
u8 byte;
@@ -546,19 +572,19 @@
/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
* generated PCIRST#. */
- byte = pmio_read(0x65);
+ byte = pm_ioread(0x65);
byte |= (1 << 4);
- pmio_write(0x65, byte);
+ pm_iowrite(0x65, byte);
/*For A13 and above. */
if (get_sb600_revision() > 0x12) {
/* rpr2.16 C-State Reset, PMIO 0x9f[7]. */
- byte = pmio_read(0x9f);
+ byte = pm_ioread(0x9f);
byte |= (1 << 7);
- pmio_write(0x9f, byte);
+ pm_iowrite(0x9f, byte);
/* rpr2.17 PCI Clock Period will increase to 30.8ns. 0x53[7]. */
- byte = pmio_read(0x53);
+ byte = pm_ioread(0x53);
byte |= (1 << 7);
- pmio_write(0x53, byte);
+ pm_iowrite(0x53, byte);
}
/* IDE Device, BDF:0-20-1 */
@@ -612,7 +638,7 @@
/*
* Compliant with CIM_48's ATSBPowerOnResetInitJSP
*/
-static void sb600_por_init()
+static void sb600_por_init(void)
{
/* sbDevicesPorInitTable + sbK8PorInitTable */
sb600_devices_por_init();
@@ -625,7 +651,7 @@
* Compliant with CIM_48's AtiSbBeforePciInit
* It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration.
*/
-static void sb600_before_pci_init()
+void sb600_before_pci_init(void)
{
sb600_pci_cfg();
}
@@ -633,7 +659,7 @@
/*
* This function should be called after enable_sb600_smbus().
*/
-static void sb600_stage1(void)
+void sb600_stage1(void)
{
printk(BIOS_INFO, "sb600_early_setup()\n");
sb600_por_init();
Modified: coreboot-v3/southbridge/amd/sb600/stage1_reset.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/stage1_reset.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/sb600/stage1_reset.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -19,6 +19,7 @@
#include <types.h>
#include <lib.h>
+#include <io.h>
#include <console.h>
#include <device/pci.h>
#include <msr.h>
@@ -29,6 +30,7 @@
void hard_reset(void)
{
+ void set_bios_reset(void);
set_bios_reset();
/* Try rebooting through port 0xcf9 */
/* Actually it is not a real hard_reset --- it only resets coherent link table, but
Modified: coreboot-v3/southbridge/amd/sb600/usb.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/usb.c 2008-10-06 17:11:47 UTC (rev 892)
+++ coreboot-v3/southbridge/amd/sb600/usb.c 2008-10-06 17:12:38 UTC (rev 893)
@@ -17,14 +17,22 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <console/console.h>
-#include <device/device.h>
+#include <types.h>
+#include <lib.h>
+#include <console.h>
#include <device/pci.h>
+#include <msr.h>
+#include <legacy.h>
#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <usbdebug_direct.h>
-#include <arch/io.h>
+#include <device/smbus.h>
+#include <cpu.h>
+#include <lapic.h>
+#include <io.h>
+#include <statictree.h>
+#include <config.h>
+#include <mc146818rtc.h>
#include "sb600.h"
+#include "sb600.h"
static struct pci_operations lops_pci = {
.set_subsystem = pci_dev_set_subsystem,
@@ -94,7 +102,7 @@
/* pci_write_config32(dev, 0xf8, dword); */
usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF);
- printk_info("usb2_bar0=%x\n", usb2_bar0);
+ printk(BIOS_INFO, "usb2_bar0=%x\n", usb2_bar0);
/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */
dword = 0x00020F00;
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