[coreboot] simple useful utility

[ron minnich]

On Fri, Oct 10, 2008 at 5:06 PM, Vincent Legoll
<vincent.legoll at gmail.com> wrote:
> Is that like what you had in mind:

This is 18:1 right?
>
> ~ # ./AMDK8MemMap.py
> 0x00:     Ox1022 - Device ID
> 0x02:     Ox1101 - Vendor ID
> 0x04:     Ox0000 - Status
> 0x06:     Ox0000 - Command
> 0x08:       Ox00 - Base CLass Code
> 0x09:       Ox00 - Subclass Code
> 0x0a:       Ox00 - Program Interface
> 0x0b:       Ox06 - Revision ID
> 0x0c:       Ox00 - Built In Self Test
> 0x0d:       Ox00 - Header Type
> 0x0e:       Ox80 - Latency Timer
> 0x0f:       Ox00 - Cache Line Size
> 0x10: Ox00000000 - Base Address 0
> 0x14: Ox00000000 - Base Address 1
> 0x18: Ox00000000 - Base Address 2
> 0x1c: Ox00000000 - Base Address 3
> 0x20: Ox00000000 - Base Address 4
> 0x24: Ox00000000 - Base Address 5
> 0x28: Ox00000000 - Card Bus CIS Pointer
> 0x2c:     Ox0000 - Subsystem ID
> 0x2e:     Ox0000 - Subsystem Vendor ID
> 0x30: Ox00000000 - ROM Base Address
> 0x34: Ox00000000 - Capabilities
> 0x38: Ox00000000 - Reserved
> 0x3c:       Ox00 - Maximum Latency
> 0x3d:       Ox00 - Minimum GNT
> 0x3e:       Ox00 - Interrupt Pin
> 0x3f:       Ox00 - Interrupt Line

0 to 40 is not really needed.
> 0x40: Ox00000003 - DRAM Base 0
> 0x44: Ox007f0000 - DRAM Limit 0
> 0x48: Ox00000000 - DRAM Base 1
> 0x4c: Ox00000001 - DRAM Limit 1
> 0x50: Ox00000000 - DRAM Base 2
> 0x54: Ox00000002 - DRAM Limit 2
> 0x58: Ox00000000 - DRAM Base 3
> 0x5c: Ox00000003 - DRAM Limit 3
> 0x60: Ox00000000 - DRAM Base 4
> 0x64: Ox00000004 - DRAM Limit 4
> 0x68: Ox00000000 - DRAM Base 5
> 0x6c: Ox00000005 - DRAM Limit 5
> 0x70: Ox00000000 - DRAM Base 6
> 0x74: Ox00000006 - DRAM Limit 6
> 0x78: Ox00000000 - DRAM Base 7
> 0x7c: Ox00000007 - DRAM Limit 7

Would be nice to convert these to actual addresses.


> 0x80: Ox00e00003 - Memory Mapped I/O Base 0
> 0x84: Ox00efff80 - Memory Mapped I/O Limit 0
> 0x88: Ox00feb003 - Memory Mapped I/O Base 1
> 0x8c: Ox00fec080 - Memory Mapped I/O Limit 1
> 0x90: Ox00000000 - Memory Mapped I/O Base 2
> 0x94: Ox00000000 - Memory Mapped I/O Limit 2
> 0x98: Ox00000000 - Memory Mapped I/O Base 3
> 0x9c: Ox00000000 - Memory Mapped I/O Limit 3
> 0xa0: Ox00000000 - Memory Mapped I/O Base 4
> 0xa4: Ox00000000 - Memory Mapped I/O Limit 4
> 0xa8: Ox00000000 - Memory Mapped I/O Base 5
> 0xac: Ox00000000 - Memory Mapped I/O Limit 5
> 0xb0: Ox00000a03 - Memory Mapped I/O Base 6
> 0xb4: Ox00000b00 - Memory Mapped I/O Limit 6
> 0xb8: Ox00800003 - Memory Mapped I/O Base 7
> 0xbc: Ox00fed300 - Memory Mapped I/O Limit 7
> 0xc0: Ox00000000 - PCI I/O Base 0
> 0xc4: Ox00000000 - PCI I/O Limit 0
> 0xc8: Ox00001013 - PCI I/O Base 1
> 0xcc: Ox000ff000 - PCI I/O Limit 1
> 0xd0: Ox00000000 - PCI I/O Base 2
> 0xd4: Ox00000000 - PCI I/O Limit 2
> 0xd8: Ox00000000 - PCI I/O Base 3
> 0xdc: Ox00000000 - PCI I/O Limit 3
> 0xe0: Oxff000003 - Configuration Base & Limit 0
> 0xe4: Ox00000000 - Configuration Base & Limit 1
> 0xe8: Ox00000000 - Configuration Base & Limit 2
> 0xec: Ox00000000 - Configuration Base & Limit 3
> 0xf0: Ox00000000 - DRAM Hole Address

This is a good start but what you are missing is the interpretation of
the fields and shifting things so we know what they really are.

That's critical. So you need to do a bit more here -- break out the
address range, shift to to show the real address, then break out the
node and cpu ids.

This is very close to what we need!

I hope the .py is not doing the config reads itself.