[coreboot] r3665 - trunk/coreboot-v2/src/southbridge/via/vt8237r

[svn at coreboot.org]

Author: cozzie
Date: 2008-10-17 04:34:06 +0200 (Fri, 17 Oct 2008)
New Revision: 3665

Modified:
   trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
Log:
Final fix for C7 boards, which are still using ROMCC, to be able to
build. As far as I know, no C7 boards currently in the tree use SPI
flash.

Signed-off-by: Corey Osgood <corey.osgood at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>



Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2008-10-17 00:06:50 UTC (rev 3664)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2008-10-17 02:34:06 UTC (rev 3665)
@@ -336,6 +336,7 @@
 	pci_write_config8(dev, 0x41, 0x7f);
 }
 
+#if defined(__GNUC__)
 void vt8237_early_spi_init(void)
 {
 	device_t dev;
@@ -358,6 +359,7 @@
 	spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c);
 	(*spireg) &= 0xff00;
 }
+#endif
 
 /* This #if is special. ROMCC chokes on the (rom == NULL) comparison.
  * Since the whole function is only called for one target and that target