[coreboot] Serengeti VGA

[Myles Watson]

On Tue, Oct 21, 2008 at 10:20 AM, Marc Jones <Marc.Jones at amd.com> wrote:

> Myles Watson wrote:
>
>
>>
>> On Mon, Oct 20, 2008 at 4:10 PM, Marc Jones <Marc.Jones at amd.com <mailto:
>> Marc.Jones at amd.com>> wrote:
>>
>>    Myles Watson wrote:
>>
>>
>>        0    6    0     AMD-8111 PCI
>>        74601022    02300147    06040007    00014000
>>        00000000    00000000    40010100    02001010
>>        FE00FD00    FFE0FFF0    00000000    00000000
>>        00000000    000000C0    00000000    042B00FF
>>
>>                                            ^
>>    ISA isn't set. That might be a problem.
>>
>>
>> I can't tell that v2 ever sets it.  In the 8111 datasheet it looks like
>> that bit makes it so that bits 8 & 9 of the address get ignored so that only
>> 256B of every 1024 are accessible.  I don't think that's what we want.
>>
>> Looking for that I found an interesting couple of defines.
>>
>> include/device/pci_def.h:#define  PCI_BRIDGE_CTL_NO_ISA   0x04    /*
>> Disable bridging of ISA ports */
>> include/device/pci_def.h:#define  PCI_CB_BRIDGE_CTL_ISA           0x04
>>
>> I can see that they're used in two different places (one for the hardware,
>> one for the device struct), but it still seems confusing.
>>
>
> I think that the problem is probably in the mmio map that Ron posted
> yesterday.
>

This is my latest.  The  one Ron posted was from func 0 just after RAM
init.  This one is from func 1.
After RAM init:
DRAM(40)0000000000-000fffffff, ->(0), R, W, No interleave, 0
DRAM(48)0000000000-0000ffffff, ->(1), , , No interleave, 0
DRAM(50)0000000000-0000ffffff, ->(2), , , No interleave, 0
DRAM(58)0000000000-0000ffffff, ->(3), , , No interleave, 0
DRAM(60)0000000000-0000ffffff, ->(4), , , No interleave, 0
DRAM(68)0000000000-0000ffffff, ->(5), , , No interleave, 0
DRAM(70)0000000000-0000ffffff, ->(6), , , No interleave, 0
DRAM(78)0000000000-0000ffffff, ->(7), , , No interleave, 0
MMIO(80)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(88)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(90)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(98)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(a0)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(a8)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(b0)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(b8)00fc000000-00ffffffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non
posted 0
PCIIO(c0)00000003-01fff000
PCIIO(c0)00000000-01fff000, ->(0,0), R, W,VGA 0 ISA 0
PCIIO(c8)00000000-00000000
PCIIO(c8)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0
PCIIO(d0)00000000-00000000
PCIIO(d0)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0
PCIIO(d8)00000000-00000000
PCIIO(d8)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0
CONFIG(e0)0000003f-00000000 ->(0,0),R W CE 0
CONFIG(e4)00000000-00000000 ->(0,0),  CE 0
CONFIG(e8)00000000-00000000 ->(0,0),  CE 0
CONFIG(ec)00000000-00000000 ->(0,0),  CE 0

After assign resources ( I took out the ones that were all 0)
DRAM(40)0000000000-000fffffff, ->(0), R, W, No interleave, 0
MMIO(a8)00000a0000-00000bffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non
posted 0
MMIO(b0)00fd000000-00fe1fffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non
posted 0
PCIIO(c0)00001000-00002000, ->(0,0), R, W,VGA 1 ISA 0
CONFIG(e0)00000003-00000000 ->(0,0),R W CE 0

Thanks,
Myles
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