[coreboot] HT revision 1.02 in K8

[Carl-Daniel Hailfinger]

On 24.10.2008 17:13, Carl-Daniel Hailfinger wrote:
> Hi,
>
> I'm getting the following message from lspci on my K8 machine:
>
> 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8
> [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100]
>         Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop-
> ParErr- Stepping- SERR- FastB2B- DisINTx-
>         Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
>         Capabilities: [80] HyperTransport: Host or Secondary Interface
>                 !!! Possibly incomplete decoding for revision 1.02
>                 Command: WarmRst+ DblEnd-
>                 Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO-
> <CRCErr=0
>                 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit
>                 Revision ID: 1.02
>         Kernel modules: ipmi_si
>
> Note the warning about "Possibly incomplete decoding" which stems from
> the fact that the processor mentions HT revision 1.02 which is the last
> non-public revision. Every revision from 1.03 and beyond seems to be
> publically available. Now the big question is: Can we decode HT 1.02
> like HT 1.03 or have there been fundamental changes in between? I'd like
> to create a patch for PCIutils (lspci) so we can have full info without
> a warning message.
>   

I forgot to specify the processor:
/proc/cpuinfo
processor       : 0
vendor_id       : AuthenticAMD
cpu family      : 15
model           : 44
model name      : AMD Sempron(tm) Processor 3000+
stepping        : 2
cpu MHz         : 1800.000
cache size      : 128 KB
fpu             : yes
fpu_exception   : yes
cpuid level     : 1
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx mmxext fxsr_opt
lm 3dnowext 3dnow up pni lahf_lm
bogomips        : 3620.86
TLB size        : 1024 4K pages
clflush size    : 64
cache_alignment : 64
address sizes   : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp tm stc

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/