[coreboot] r957 - in coreboot-v3: northbridge/amd/k8 southbridge/amd/sb600 southbridge/nvidia/mcp55
svn at coreboot.org
svn at coreboot.org
Tue Oct 28 17:06:28 CET 2008
Author: myles
Date: 2008-10-28 17:06:28 +0100 (Tue, 28 Oct 2008)
New Revision: 957
Modified:
coreboot-v3/northbridge/amd/k8/coherent_ht.c
coreboot-v3/northbridge/amd/k8/domain.c
coreboot-v3/southbridge/amd/sb600/stage1_smbus.c
coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
Log:
Trivial fixes of printk_debug and a comment from v2.
Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>
Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-10-28 02:06:15 UTC (rev 956)
+++ coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-10-28 16:06:28 UTC (rev 957)
@@ -1503,12 +1503,7 @@
nodes = setup_smp8();
#endif
-#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("%02x nodes initialized.\r\n", nodes);
-#else
- print_debug_hex8(nodes);
- print_debug(" nodes initialized.\r\n");
-#endif
+ printk(BIOS_DEBUG,"%02x nodes initialized.\r\n", nodes);
return nodes;
}
Modified: coreboot-v3/northbridge/amd/k8/domain.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/domain.c 2008-10-28 02:06:15 UTC (rev 956)
+++ coreboot-v3/northbridge/amd/k8/domain.c 2008-10-28 16:06:28 UTC (rev 957)
@@ -259,7 +259,7 @@
#if 1
#warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
- /* Round the mmio hold to 64M */
+ /* Round the mmio hole to 64M */
mmio_basek &= ~((64*1024) - 1);
#endif
Modified: coreboot-v3/southbridge/amd/sb600/stage1_smbus.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/stage1_smbus.c 2008-10-28 02:06:15 UTC (rev 956)
+++ coreboot-v3/southbridge/amd/sb600/stage1_smbus.c 2008-10-28 16:06:28 UTC (rev 957)
@@ -196,7 +196,7 @@
tmp &= ~mask;
tmp |= val;
- /* printk_debug("about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
+ /* printk(BIOS_DEBUG,"about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
outl(tmp, AB_DATA);
}
Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-10-28 02:06:15 UTC (rev 956)
+++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-10-28 16:06:28 UTC (rev 957)
@@ -224,7 +224,7 @@
// reg |= (1<<0);
reg &= ~(0x3f<<4);
if (reg != reg_old) {
- printk_debug("mcp55.c pcie enabled\n");
+ printk(BIOS_DEBUG,"mcp55.c pcie enabled\n");
pci_write_config32(sm_dev, 0xe4, reg);
}
#endif
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