[coreboot] v2: The elfboot process with 128MB RAM
Mats Erik Andersson
mats.andersson at gisladisker.se
Thu Sep 11 02:04:29 CEST 2008
Dear Tim ter Laak,
I certainly appreciate your company in out quest for knowledge!
> So long as I didn't change the values hardcoding the 64 MB limit, I could
> boot fine into the payload, even with all three DIMMs present. With the
> changes in raminit.c, elfboot/Coreinfo stops with an exception 6 (illegal
> opcode), as per the log below.
Here the higher memory devices were simply ignored. Thus no interference.
> differences. My prime suspect for now is the Memory Buffer Strength
> Control Register (0x69-0x6e), but I haven't had the chance to test that
> yet, and am not certain by a long shot that it's it. I'm including the
> dumps below, in case you can use them to better understand the problem
> with your own board.
> Unfortunately, setting the MBSC Registers to values that work in the warm
> reboot doesn't get me any further. I have noticed however that I don't
> always get exception 6, but also 13 (general protection error), or just a
> hang with no exception message. I'll continue to look further.
My logging reveals results identical to yours, and there is either a blind
halt, exceptions 6 or 13, and as of lately a reproducable exception -1.
At present I am experimenting with these settings:
pci_write_config16(ctrl->d0, RPS, 0x0055); // Always 4kB page size.
pci_write_config16(ctrl->d0, SDRAMC, 0x0103);
/* Only devices with two banks, until tested to be four banks. */
data = 0x00;
if ( spd_read_byte(ctrl->channel0[0], 17) == 0x04 )
data |= 0x03;
if ( spd_read_byte(ctrl->channel0[1], 17) == 0x04 )
data |= (0x03 << 2);
/* The value (data << 8) produces correct bank flags for PGPOL. */
pci_write_config16(ctrl->d0, PGPOL, 0x07 | (data << 8));
pci_write_config32(ctrl->d0, MBSC, 0x0003c003);
Apart from the dynamic bank/row detection, these are the only settings
that I am manipulating at present.
One remarkable observation is that with these and similar settings,
two double-sided 128MB cards with identical SPD-data 0x00 to 0x3d
produce disparate results: one of them verifies RAM from 1MB to 128MB--,
whereas the other verifies only 1MB to 64MB--. Explanation anyone?
They support latency CL3 and CL2. Another 128MB double-sided card
which only supports CL3, is still verifying all 128MB of RAM.
I suspect that the burst length must be understood better, as well
as the strobe signals, but I find my present references to be
insufficient at the moment.
Best regards for now,
Mats E Andersson
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