[coreboot] r869 - in coreboot-v3: mainboard/amd/serengeti northbridge/amd/k8

svn at coreboot.org svn at coreboot.org
Fri Sep 19 22:00:17 CEST 2008


Author: rminnich
Date: 2008-09-19 22:00:17 +0200 (Fri, 19 Sep 2008)
New Revision: 869

Modified:
   coreboot-v3/mainboard/amd/serengeti/initram.c
   coreboot-v3/northbridge/amd/k8/dqs.c
   coreboot-v3/northbridge/amd/k8/raminit.c
Log:
Continue cleanup. Still boots to etherboot in simnow. 

Far fewer warnings than before :-)

TODO: Document the DIMM_SETTINGS variable. 
FIx up fidvid code. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: coreboot-v3/mainboard/amd/serengeti/initram.c
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/initram.c	2008-09-19 18:35:22 UTC (rev 868)
+++ coreboot-v3/mainboard/amd/serengeti/initram.c	2008-09-19 20:00:17 UTC (rev 869)
@@ -126,6 +126,7 @@
 	void enable_smbus(void);
 	void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn);
 	void soft_reset_x(unsigned sbbusn, unsigned sbdn);
+	int cpu_init_detected(unsigned int nodeid);
 	u32 init_detected;
 	static const u16 spd_addr[] = {
 		//first node
@@ -151,11 +152,15 @@
 	int needs_reset;
 	unsigned bsp_apicid = 0;
 	struct msr msr;
+	struct node_core_id me;
 
-	printk(BIOS_DEBUG, "Hi there from stage1\n");
+	me = get_node_core_id();
+	printk(BIOS_DEBUG, "Hi there from stage1, cpu%d, core%d\n", me.nodeid, me.coreid);
 	post_code(POST_START_OF_MAIN);
 	sysinfo = &(global_vars()->sys_info);
 
+	init_detected = cpu_init_detected(me.nodeid);
+	printk(BIOS_DEBUG, "init_detected: %d\n", init_detected);
 	/* well, here we are. For starters, we need to know if this is cpu0 core0. 
 	 * cpu0 core 0 will do all the DRAM setup. 
 	 */

Modified: coreboot-v3/northbridge/amd/k8/dqs.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/dqs.c	2008-09-19 18:35:22 UTC (rev 868)
+++ coreboot-v3/northbridge/amd/k8/dqs.c	2008-09-19 20:00:17 UTC (rev 869)
@@ -41,8 +41,6 @@
 //0: mean no debug info
 #define DQS_TRAIN_DEBUG 0
 
-// always undef this. We only support F2 and later. 
-#undef K8_REV_F_SUPPORT_F0_F1_WORKAROUND
 u32 pci_read_config32_index(u32 dev, u32 index_reg, u32 index);
 void pci_write_config32_index(u32 dev, u32 index_reg, u32 index, u32 data);
 u32 pci_read_config32_index_wait(u32 dev, u32 index_reg, u32 index);
@@ -559,10 +557,6 @@
 
 
 	if(Pass == DQS_FIRST_PASS) {
-#ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND
-	cpu_f0_f1 = is_cpu_pre_f2_in_bsp(ctrl->node_id);
-	if(!cpu_f0_f1) 
-#endif
 	{
 #if 1
 		/* Set the DqsRcvEnTrain bit */
@@ -870,9 +864,6 @@
         pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword);
 
 	if(Pass == DQS_FIRST_PASS) {
-#ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND
-	if(!cpu_f0_f1) 
-#endif
 	{
 		dword = pci_conf1_read_config32(ctrl->f2, DRAM_CTRL);
 	        dword &= ~DC_DqsRcvEnTrain;
@@ -1650,77 +1641,6 @@
 	
 }
 
-#ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND
-static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl, u64 *tsc0, struct sys_info *sysinfo)
-{
-        u64 tsc1[8];
-	unsigned cpu_f0_f1[8];
-	int i;
-
-	if (DQS_TRAIN_DEBUG) {
-	        printk(BIOS_DEBUG, "dqs_timing: tsc1[8] :0x%llx", tsc1);
-	}
-
-        for(i = 0; i < controllers; i++) {
-                if (!sysinfo->ctrl_present[i])
-                        continue;
-
-                /* Skip everything if I don't have any memory on this controller */
-		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
-
-                u32 dword;
-
-                cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i);
-
-                if(!cpu_f0_f1[i]) continue;
-
-                dword = pci_conf1_read_config32(ctrl[i].f2, DRAM_CTRL);
-                dword &= ~DC_DqsRcvEnTrain;
-                pci_conf1_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
-
-                dword = pci_conf1_read_config32(ctrl[i].f2, DRAM_INIT);
-                dword |= DI_EnDramInit;
-                pci_conf1_write_config32(ctrl[i].f2, DRAM_INIT, dword);
-                dword &= ~DI_EnDramInit;
-                pci_conf1_write_config32(ctrl[i].f2, DRAM_INIT, dword);
-
-                tsc1[i] = cycles();
-                print_debug_dqs_tsc("begin: tsc1", i, tsc1[i].hi, tsc1[i].lo, 2);
-
-                dword = tsc1[i].lo + tsc0[i].lo;
-                if((dword<tsc1[i].lo) || (dword<tsc0[i].lo)) {
-                        tsc1[i].hi++;
-                }
-                tsc1[i].lo = dword;
-                tsc1[i].hi+= tsc0[i].hi;
-
-                print_debug_dqs_tsc("end  : tsc1", i, tsc1[i].hi, tsc1[i].lo, 2);
-
-        }
-
-        for(i = 0; i < controllers; i++) {
-                if (!sysinfo->ctrl_present[i])
-                        continue;
-
-                /* Skip everything if I don't have any memory on this controller */
-		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
-
-		if(!cpu_f0_f1[i]) continue;
-
-                u64 tsc;
-
-                do {
-                        tsc = cycles();
-                } while ((tsc1[i].hi>tsc.hi) || ((tsc1[i].hi==tsc.hi) && (tsc1[i].lo>tsc.lo)));
-
-                print_debug_dqs_tsc("end  : tsc ", i, tsc.hi, tsc.lo, 2);
-        }
-
-}
-
-#endif
-
-
 /* setting variable mtrr, comes from linux kernel source */
 static void set_var_mtrr_dqs(
         unsigned int reg, unsigned long basek, unsigned long sizek,
@@ -1927,12 +1847,7 @@
 
 #if MEM_TRAIN_SEQ == 0
 
-
-#ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND
-static void dqs_timing(int controllers, const struct mem_controller *ctrl, u64 *tsc0, struct sys_info *sysinfo)
-#else
 void dqs_timing(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo)
-#endif
 {
 	int  i;
 
@@ -1969,9 +1884,6 @@
         }
 
 	tsc[1] = cycles();
-#ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND
-	f0_svm_workaround(controllers, ctrl, tsc0, sysinfo);
-#endif
 
 	tsc[2] = cycles();
         for(i = 0; i < controllers; i++) {

Modified: coreboot-v3/northbridge/amd/k8/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/raminit.c	2008-09-19 18:35:22 UTC (rev 868)
+++ coreboot-v3/northbridge/amd/k8/raminit.c	2008-09-19 20:00:17 UTC (rev 869)
@@ -46,8 +46,7 @@
 #warning where to we define supported DIMM types
 #define DIMM_SUPPORT 0x0104
 
-/* we won't support the buggy old chips */
-#undef K8_REV_F_SUPPORT_F0_F1_WORKAROUND
+/* NOTE: F2 and later ONLY */
 inline void print_raminit(const char *strval, u32 val)
 {
         printk(BIOS_DEBUG, "%s%08x\n", strval, val);
@@ -2750,13 +2749,6 @@
 	int i;
 	void dqs_timing(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo);
 	void memreset(int controllers, const struct mem_controller *ctrl);
-#ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND
-        unsigned cpu_f0_f1[8];
-	/* FIXME: How about 32 node machine later? */
-	tsc_t tsc, tsc0[8];
-	
-	print_debug_addr("sdram_enable: tsc0[8]: ", &tsc0[0]);
-#endif
 
 	/* Error if I don't have memory */
 	if (memory_end_k(ctrl, controllers) == 0) {
@@ -2817,20 +2809,6 @@
 			pci_conf1_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
 		}
 
-#ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND
-	        cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i);
-	        if(cpu_f0_f1[i]) {
-			//Rev F0/F1 workaround
-#if 1
-			        /* Set the DqsRcvEnTrain bit */
-		        dword = pci_conf1_read_config32(ctrl[i].f2, DRAM_CTRL);
-		        dword |= DC_DqsRcvEnTrain;
-		        pci_conf1_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
-#endif
-			tsc0[i] = rdtsc();			
-		}
-#endif
-
 #if 0
                                /* Set the DqsRcvEnTrain bit */
                         dword = pci_conf1_read_config32(ctrl[i].f2, DRAM_CTRL);
@@ -2870,25 +2848,6 @@
 			dcm = pci_conf1_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
 		} while(((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ );
 
-#ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND
-		if(cpu_f0_f1[i]) {
-	                tsc= rdtsc();
-
-			print_debug_dqs_tsc("\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2); 
-			print_debug_dqs_tsc("end   tsc ", i, tsc.hi, tsc.lo, 2); 
-
-        	        if(tsc.lo<tsc0[i].lo) {
-                	        tsc.hi--;
-	                }
-        	        tsc.lo -= tsc0[i].lo;
-	                tsc.hi -= tsc0[i].hi;
-
-        	        tsc0[i].lo = tsc.lo;
-	                tsc0[i].hi = tsc.hi;
-
-        	        print_debug_dqs_tsc("     dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
-		}
-#endif
 		printk(BIOS_DEBUG, " done\n");
 	}
 
@@ -2925,11 +2884,7 @@
 
 
 #if MEM_TRAIN_SEQ ==  0
-   #ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND
-	dqs_timing(controllers, ctrl, tsc0, sysinfo);
-   #else
 	dqs_timing(controllers, ctrl, sysinfo);
-   #endif
 #else
 
    #if MEM_TRAIN_SEQ == 2





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