[coreboot] VIA Epia-MII stuff
c-d.hailfinger.devel.2006 at gmx.net
Fri Apr 3 14:18:40 CEST 2009
On 03.04.2009 13:54, Stefan Reinauer wrote:
> On 03.04.2009, at 13:29, wrote:
>> On Fri, Apr 03, 2009 at 12:50:00PM +0200, Peter Stuge wrote:
>>> Markus T�rnqvist wrote:
>>>> So I tried ROM_SIZE=192*1024
>>>> Heh, and this should end up on the wiki in some non-confusing
>>>> format too so the next guy won't have to ask the same questions :)
>>> The exact way the five or ten different SIZE options in v2 interact
>>> is still a mystery to me after many years of occasional tweaking.
>>> It's horrible.
>> I'll try to test v3 when the epia-mii gets some support there :)
> It's unlikely to ever see that happen.. The c3, unlike the c7, is said
> to be incapable of Cache As Ram... That's the reason v3 looks so much
> simpler, it will never support CPUs without CAR capability..
I still hope CAR can be made to work on the C3. IIRC C3 CAR was "just"
totally unreliable and not broken. To be honest, with our current CAR
code, it is very easy to break it by accident (even in v3) and I suspect
that happened when testing C3 CAR. And even if we get CAR to work
reliably on the C3, it will be extremely _slow_ (maybe even slower than
with ROMCC) until RAM is turned on.
More information about the coreboot