[coreboot] [v2] r4092 - trunk/util/flashrom

[svn at coreboot.org]

Author: uwe
Date: 2009-04-11 15:59:00 +0200 (Sat, 11 Apr 2009)
New Revision: 4092

Modified:
   trunk/util/flashrom/README
   trunk/util/flashrom/flashrom.8
Log:
Mention a few more flash chip packages in README/manpage.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/util/flashrom/README
===================================================================
--- trunk/util/flashrom/README	2009-04-10 23:02:48 UTC (rev 4091)
+++ trunk/util/flashrom/README	2009-04-11 13:59:00 UTC (rev 4092)
@@ -5,8 +5,9 @@
 Flashrom is a utility for reading, writing, and erasing flash ROM chips.
 It's often used to flash BIOS/coreboot/firmware images.
 
-It supports a wide range of DIP32, PLCC32, DIP8, and TSOP chips, which use
-various protocols such as LPC, FWH, parallel flash, or SPI.
+It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and
+TSOP40 chips, which use various protocols such as LPC, FWH, parallel flash,
+or SPI.
 
 (see http://coreboot.org for details on coreboot)
 

Modified: trunk/util/flashrom/flashrom.8
===================================================================
--- trunk/util/flashrom/flashrom.8	2009-04-10 23:02:48 UTC (rev 4091)
+++ trunk/util/flashrom/flashrom.8	2009-04-11 13:59:00 UTC (rev 4092)
@@ -1,6 +1,6 @@
-.TH FLASHROM 8 "January 5, 2009"
+.TH FLASHROM 8 "April 11, 2009"
 .SH NAME
-flashrom \- utility for reading, writing, and erasing BIOS/ROM/flash chips
+flashrom \- read, write, and erase BIOS/ROM/flash chips
 .SH SYNOPSIS
 .B flashrom \fR[\fB\-rwvEVfLhR\fR] [\fB\-c\fR chipname] [\fB\-s\fR exclude_start] [\fB\-e\fR exclude_end]
          [\fB-m\fR vendor:part] [\fB-l\fR file.layout] [\fB-i\fR image_name] [file]
@@ -9,8 +9,9 @@
 is a utility for reading, writing, and erasing flash ROM chips.
 It's often used to flash BIOS/coreboot/firmware images.
 .PP
-It supports a wide range of DIP32, PLCC32, DIP8, and TSOP chips, which use
-various protocols such as LPC, FWH, parallel flash, or SPI.
+It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and
+TSOP40 chips, which use various protocols such as LPC, FWH, parallel flash,
+or SPI.
 .PP
 (see
 .B http://coreboot.org