[coreboot] [v2] r4585 - trunk/coreboot-v2/src/southbridge/amd/rs690
svn at coreboot.org
svn at coreboot.org
Wed Aug 26 18:04:47 CEST 2009
Author: mjones
Date: 2009-08-26 18:04:47 +0200 (Wed, 26 Aug 2009)
New Revision: 4585
Modified:
trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c
trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c
Log:
Enable Direct TMDS for the RS690, which allows to display on HDMI and DVI
monitors.
Signed-off-by: Libra Li <libra.li at technexion.com>
Acked-by: Marc Jones <marcj303 at gmail.com>
Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c 2009-08-26 15:35:36 UTC (rev 4584)
+++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c 2009-08-26 16:04:47 UTC (rev 4585)
@@ -471,7 +471,49 @@
/* done by enable_pci_bar3() before */
/* step 6 SBIOS compile flags */
+ if (cfg->gfx_tmds) {
+ /* step 6.2.2 Clock-Muxing Control */
+ /* step 6.2.2.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
+ /* step 6.2.2.2 */
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
+
+ /* step 6.2.2.3 */
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
+
+ /* step 6.2.3 Lane-Muxing Control */
+ /* step 6.2.3.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
+
+ /* step 6.2.4 Received Data Control */
+ /* step 6.2.4.1 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
+
+ /* step 6.2.4.2 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
+
+ /* step 6.2.4.3 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
+
+ /* step 6.2.4.4 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
+
+ /* step 6.2.5 PLL Power Down Control */
+ /* step 6.2.5.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
+
+ /* step 6.2.6 Driving Strength Control */
+ /* step 6.2.6.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
+
+ /* step 6.2.6.2 */
+ set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
+ }
+
+ printk_info("rs690_gfx_init step6.\n");
+
/* step 7 compliance state, (only need if CMOS option is enabled) */
/* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
if (cfg->gfx_compliance) {
Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c 2009-08-26 15:35:36 UTC (rev 4584)
+++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c 2009-08-26 16:04:47 UTC (rev 4585)
@@ -87,18 +87,21 @@
Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS +
PCIE_GFX_COMPLIANCE))) {
}
- /* step 3 Power Down Control for Southbridge */
- reg = nbpcie_p_read_index(dev, 0xa2);
- switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */
- case 1:
- nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
- break;
- case 2:
- nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
- break;
- default:
- break;
+ if (!cfg->gfx_tmds){
+ /* step 3 Power Down Control for Southbridge */
+ reg = nbpcie_p_read_index(dev, 0xa2);
+
+ switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */
+ case 1:
+ nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
+ break;
+ case 2:
+ nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
+ break;
+ default:
+ break;
+ }
}
}
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