[coreboot] #129: Add support for high_tables_base for all chipsets that don't support it yet.

coreboot svn at coreboot.org
Thu Dec 17 23:25:16 CET 2009


#129: Add support for high_tables_base for all chipsets that don't support it
yet.
---------------------------------+------------------------------------------
   Reporter:  oxygene            |          Owner:  stepan
       Type:  defect             |         Status:  new   
   Priority:  critical           |      Milestone:        
  Component:  coreboot           |        Version:  v2    
   Keywords:                     |   Dependencies:        
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------

Comment(by bam <mybigspam@…>):

 If I have CONFIG_HAVE_HIGH_TABLES = 1 (or CONFIG_WRITE_HIGH_TABLES=1),
 etherboot payload can't work:
 {{{
 High Tables Base is 3ff0000.
 Moving GDT to 0x3ff0000...ok
 Writing high table forward entry at 0x00000500
 Wrote coreboot table at: 00000500 - 00000518  checksum f7df
 New low_table_end: 0x00000518
 Now going to write high coreboot table at 0x03ff0400
 rom_table_end = 0x03ff0400
 Adjust low_table_end from 0x00000518 to 0x00001000
 Adjust rom_table_end from 0x03ff0400 to 0x04000000
 Adding high table area
 Wrote coreboot table at: 03ff0400 - 03ff0a34  checksum 169b
 Check fallback/coreboot_ram
 Check fallback/payload
 Got a payload
 Loading segment from rom address 0xfffc61f8
   data (compression=1)
   New segment dstaddr 0x10000 memsize 0xab80 srcaddr 0xfffc6230 filesize
 0x44c0
   (cleaned up) New segment addr 0x10000 size 0xab80 offset 0xfffc6230
 filesize 0x44c0
 Loading segment from rom address 0xfffc6214
   Entry Point 0x000100b0
 Loading Segment: addr: 0x0000000000010000 memsz: 0x000000000000ab80
 filesz: 0x00000000000044c0
 Post relocation: addr: 0x0000000000010000 memsz: 0x000000000000ab80
 filesz: 0x00000000000044c0
 using LZMA
 Clearing Segment: addr: 0x0000000000014690 memsz: 0x00000000000064f0
 dest 10000, end 1ab80, bouncebuffer 3fbc000
 Jumping to boot code at 100b0
 CPU 1345 Mhz
 Etherboot 5.4.4 (GPL) http://etherboot.org
 Drivers: VIA 86C100   Images: ELF
 Protocols: BOOTP NFS
 init_heap: No heap found.
 }}}
 ..and halts.[[BR]]
 Tested on qemu and epia-m.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/129#comment:2>
coreboot <http://www.coreboot.org/>



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