[coreboot] Problems porting H8dmr_fam10 to H8qme-2+

Knut Kujat knuku at gap.upv.es
Fri Dec 18 16:41:23 CET 2009


Myles Watson escribió:
>
>     It turns out that the problem is before the print statements I
>     inserted.  For some reason, your domain's IO resource is only
>     giving you 0x7ff of IO space.  That's not enough.  I can't see
>     anywhere in the code where that would be coming from, so I'm
>     assuming memory corruption.  At this point the limit should still
>     be 0000ffff.
>
>     Could you try increasing the stack and heap sizes?  If that
>     doesn't work we'll have to find where the limit is getting
>     changed, since it's correct the first time that the resources are
>     printed.
>
>      PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff
> flags c0000100 index 60
>      PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags
> c0000400 index 70
>
>      PNP: 002e.3 links 0 child on link 0 NULL
>      PNP: 002e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags
> 100 index 60
>      PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags
> 400 index 70
> ...
> PCI: 00:06.2 20 *  [0x1cf0 - 0x1cff] io
> PNP: 002e.3 60 *  [0x2000 - 0x2007] io
>
> Never mind about the memory corruption.  PNP: 002e.3 has some
> resources that aren't "fixed", so the allocator is trying to allocate
> them.  In the SuperIO code where those resources are declared, set the
> flags to match the other resources.
Problem solved I killed it :) means I disabled it in the device tree.
The H9DMR board has two serials and my board H8QME has only one.

Now, I've got till the MTRR initialization and here is my reward:

POST: 0x93
Setting up local apic... apic_id: 0x0a done.
POST: 0x9b
CPU model: Quad-Core AMD Opteron(tm) Processor 8350
siblings = 03, CPU #10 initialized
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 00:02.0 init
Unexpected Exception: 6 @ 10:00207ff1 - Halting
Code: 0 eflags: 00010046
eax: 00000000 ebx: 00226358 ecx: 0021ea74 edx: 00000001
edi: 0021ea74 esi: 00000001 ebp: 0023fff4 esp: 0023ff50
POST: 0xff

the strange thing is that it seems to work for like 11 other cores. And
this log is from my last try but before it always starts rebooting with
SOFT RESET after:
MTRR check
Fixed MTRRs   : Enabled

Attached there is the whole log its getting bigger but still not till
the end :(

THX,
Knut Kujat.

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20091218/9fe92604/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: Coreboot.log
Type: text/x-log
Size: 153163 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20091218/9fe92604/attachment.log>


More information about the coreboot mailing list