[coreboot] Problems porting H8dmr_fam10 to H8qme-2+

Myles Watson mylesgw at gmail.com
Mon Dec 28 17:54:53 CET 2009


On Mon, Dec 28, 2009 at 3:26 AM, Knut Kujat <knuku at gap.upv.es> wrote:

> Myles Watson escribió:
> >>> Scan for VGA option rom
> >>> Got ps2 nak (status=51); continuing
> >>> ps2_recvbyte timeout
> >>>
> >>> I can't see your VGA ROM getting run anywhere.  Did I just miss it?
> >>>
> >> Nop, not working anywhere seems like Seabios doesn't find any vga rom.
> >>
> > You could try a more verbose setting for SeaBIOS and send the output to
> > Kevin.  I'm surprised it doesn't just work.
> >
> >
> >> So I tried setting up CONFIG_SB_HT_CHAIN_ON_BUS0 to different values, no
> >> luck!
> >>
> > Yeah.  It doesn't seem like an enumeration problem.  The device tree
> seems
> > like it's getting set up pretty well.
> >
> >
> >>> You could try having Coreboot run it with vm86 and with
> >>> CONFIG_CONSOLE_VGA set to see if that works.  I'm wondering why
> >>> SeaBIOS isn't finding it.
> >>>
> >>>
> >> CONFIG_CONSOLE_VGA was already set to 1. How do I run coreboot with
> vm86?
> >>
> > CONFIG_VGA_ROM_RUN =1
> > In Kconfig there's a VM86 option, but I don't see it in newconfig.
> >
> >
> >> At least now at linux boot up my NICs are found but trying to initialize
> >> they got to a "Unable to allocate interrupt" :( I attach my latest log.
> >>
> > Did you change the mptable and irqtables to match the factory
> assignments?
> >
> I thought they got set up by code and I don't have to touch anything. Am
> I wrong? If so what and where do I have to do changes since mptable.c
> and irq_table.c is all code.
>

in mptable.c:

        dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
        if (dev) {
            res = find_resource(dev, PCI_BASE_ADDRESS_1);
            if (res) {
                smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
            }

/* These three values are interrupt routing values. */
            dword = 0x43c6c643;
            pci_write_config32(dev, 0x7c, dword);

            dword = 0x81001a00;
            pci_write_config32(dev, 0x80, dword);

            dword = 0xd00012d2;
            pci_write_config32(dev, 0x84, dword);

        }

Unfortunately, it's undocumented, so you have a couple of options:
1. Look at http://www.coreboot.org/Nvidia_MCP55_Porting_Notes
2. Decode the ACPI interrrupt assignments

Either way you may need to look at the interrupt assignments in Linux when
booted with the factory BIOS.

I attached a log with seabios set up on debug level 6,


That was high enough.  You can also change the debugging level of any
component in config.h


More information about the coreboot mailing list