[coreboot] Gigabyte M57SLI-S4 PCI-Initialisation Problems
echelon at free.fr
Sun Feb 8 12:54:18 CET 2009
Of course, I would like to contribute again to the coreboot project, but
unfortunately last year I had many personal problems to deal with and not much
time for coreboot.. :/
For your questions:
*1) Probing the PCI bus was usefull to figure out that the "GPIO multiplexer" of
the SB was misconfigured, and the PCI configuration requests weren't understood
by a card plugged in the first PCI slot. I didn't have time to do the same test
for the second PCI slot. What is a little disturbing is that after patching the
coreboot code with GPIO configuration values extracted from the proprietary BIOS
configuration, the second PCI slot is still unfunctional. So, indeed I think
that it is necessary to probe the second PCI slot.. (If you don't have access to
a good oscilloscope, I can do this test maybe later next week, let me know..)
*4) Unfortunately I lost this little quickie, but it is not very complicated to
write from scratch.. What you need to do:
-1) after booting under Linux/legacy_BIOS, read the SYSCTRL_REG (0x64?) of the
00:01.1 PCI device (the LPC bridge?) to verify that it holds the value 0x1400.
-2) write a little program which dumps 256 bytes from the IO address 0x1400 (of
course you have to adjust the iopl of your program in order to have access to
the IO space..)
I would try to re-activate my coreboot test platforms this week.. If you have
further questions, Im will try to help you..
Quoting Harald Gutmann <harald.gutmann at gmx.net>:
> ---------- Forwarded Message ----------
> Subject: Gigabyte M57SLI-S4 PCI-Initialisation Problems
> Date: Saturday 07 February 2009
> From: Harald Gutmann <harald.gutmann at gmx.net>
> To: echelon at free.fr
> Hello Florentin,
> some times ago you figured out how to get some PCI ports on the Gigabyte
> board initialized. One Port worked with your patch as it should and gets
> interrupts, but the other one doesn't. Also there are until now some problems
> existing with the PCI-E ports.
> As time passed by there is until now no solution for the second PCI port and
> for the PCI-E interrupt problems.
> After finishing my school, and finding some good job i've more time to work
> things i'm interested, such as coreboot.
> For the following i refer on your post from October 2007 on the LinuxBios
> Mailinglist: http://www.coreboot.org/pipermail/linuxbios/2007-
> My questions to that posting:
> *1) Is it necessary/useful to measure somethings on the PCI-bus with an
> *4) Do you have the source for that simple custom utility you wrote that time
> to dump the SYSCTRL_REG which you mention in *3)?
> I and some other coreboot users are interested in trying to fix that issues
> with coreboot on this mainboard, and i hope you can help us a bit.
> Tanks in advance,
> kind regards,
> Harald Gutmann
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