[coreboot] slow load times
kevin at koconnor.net
Thu Feb 19 04:30:38 CET 2009
On Wed, Feb 18, 2009 at 07:51:33PM -0700, Myles Watson wrote:
> > > > #define CONFIG_OPTIONROMS_DEPLOYED 0
> Maybe we should modify buildrom so that this is the default when using
I think we should.
> > The current code is in src/pci.h in the foreachpci macro and in
> > src/pci.c in the pci_next() function. If there is a better way to
> > scan, please let me know.
> It's a fine way to scan. The problem is that there is no logical connection
> from bus 0 to bus 0x40 on my machine. It happens because there are multiple
> links on the Opterons. For desktop machines, many times there is only one
> link that goes to the chipset, but servers and workstations sometimes have
Well, that's a pain. I'm surprised they didn't just put a dummy
bridge entry on bus 0 that points to bus 0x40 -- it'd make scanning
You could change the pciforeach macro from:
for (MAX=0x0100, BDF=pci_next(0, &MAX) \
for (MAX=0x4000, BDF=pci_next(0, &MAX) \
that would cause it to pull in your second bridge. It will do a bit
more scanning, but that may be inevitable.
> > So, is it working now?
> I'm still having ACPI troubles, so I'm not booting into Windows yet. That's
> where I'm trying to get. At this point it's not SeaBIOS's fault, though.
> So yes, as far as I can tell right now it's working perfectly. Thanks for
> all the help.
No problem - I'm glad you're making progress. :-)
More information about the coreboot