[coreboot] slow load times
stepan at coresystems.de
Thu Feb 19 12:32:31 CET 2009
Kevin O'Connor wrote:
> On Wed, Feb 18, 2009 at 08:42:04PM -0700, Myles Watson wrote:
>>> for (MAX=0x4000, BDF=pci_next(0, &MAX) \
>> For my own use I can hard code something pretty easily. The general
>> case is much harder.
> We can add a CONFIG_PCI_MAX_ROOT_BUS setting to SeaBIOS' config.h
> If we don't want to compile in a max, and it's not reasonable to
> autodetect it, then I guess we could have coreboot pass in the max to
> SeaBIOS via the coreboot table.
Maybe coreboot should pass its complete device tree in the coreboot
table, so SeaBIOS and others can do more queries if needed? (And, for
example, scan the buses that are known to exist instead of just going
for a max.)
> Finally, I suppose SeaBIOS could just scan all 256 buses. (Does
> anyone know if a bus is guaranteed to have a device 0? If so, that
> would speed the scan significantly.)
I think to remember the PCI specification suggests so. In practice I
have seen many cards, bridges, systems where this is not the case though.
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