[coreboot] Flash chips and "page" (Was: How to find out "page size" of a flash chip?)

[Carl-Daniel Hailfinger]

On 04.01.2009 10:20, FENG Yu Ning wrote:
> On 11/19/08, Peter Stuge <peter at stuge.se> wrote:
>   
>> The page_size member is considered an eraseblock size by the code.
>>     
>
> On Wed, Nov 19, 2008 at 8:36 PM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>   
>> Yes. We should have one eraseblock_size member and one write_size member.
>>     
>
> In the flashchips array, the value of page_size is page size if the
> chip has page-write as the only write command. At other times, it is
> just a parameter of the memory geometry - maybe erase block size,
> maybe not.
>
> I have made some investigation to figure out the above result. I am
> attaching it below for convenience of further discussion.
>
> Vendor    Model            Type      Visibleness
> -----------------------------------------------------------------------
>                            S P  L F   Wr Wp
>                              Px       Ar Ap
>                              Po          1p
>                                          Zp
>                                       ?r ?p
>
> S  = SPI
>
> P  = Parallel
>      (did not seperate parallel into sub-types when investigating
>       those flash chips)
>
> L  = LPC
>
> F  = FWH
>
> Wr = Page read can start at any address within a page and will wrap
>      back at page boundary in one page read instruction
>   


Almost all SPI chips wrap at chip boundary for reads, not page boundary.
Some LPF/FWH chips do the same.


> Wp = Page program can start at any address within a page and will wrap
>      back at page boundary in one page program instruction
>   

Program wraparound (chip/page) not only depends on the chip, but also on
the programming mode. Once we introduce drivers for external flashers,
this becomes important.

We need multiple tuples of
erase function <-> erase block size <-> access mode
write function <-> write block size <-> access mode
read function <-> read block size <-> access mode

For a chip supporting multiple erase functions, this means we need
multiple erase function <-> erase block size pairs.

And each function also needs to be annotated with the access method
(LPC/FWH/SPI/special AAI/...) so that flashrom can decide on whether a
given flash function is usable with the available hardware. For example,
an external flasher may be able to use AAI mode, whereas this is
generally not possible (exceptions may apply) for in-circuit flashing
(which is used by flashrom right now).


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/