[coreboot] r1106 - coreboot-v3/northbridge/intel/i945
svn at coreboot.org
svn at coreboot.org
Thu Jan 8 17:01:25 CET 2009
Author: uwe
Date: 2009-01-08 17:01:25 +0100 (Thu, 08 Jan 2009)
New Revision: 1106
Modified:
coreboot-v3/northbridge/intel/i945/i945.h
coreboot-v3/northbridge/intel/i945/raminit.c
coreboot-v3/northbridge/intel/i945/rcven.c
Log:
Port relevant parts of r3741 from v2 to v3 (build-tested on v3):
Merge some parts of the i945 review (trivial):
* fix \r\n occurence in i945 code
* drop early TOLUD write
* fix 16bit BCTRL1 access
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
Modified: coreboot-v3/northbridge/intel/i945/i945.h
===================================================================
--- coreboot-v3/northbridge/intel/i945/i945.h 2009-01-08 15:44:56 UTC (rev 1105)
+++ coreboot-v3/northbridge/intel/i945/i945.h 2009-01-08 16:01:25 UTC (rev 1106)
@@ -67,7 +67,7 @@
/* Device 0:1.0 PCI configuration space (PCI Express) */
-#define BCTRL1 0x3e /* 8bit */
+#define BCTRL1 0x3e /* 16bit */
/* Device 0:2.0 PCI configuration space (Graphics Device) */
Modified: coreboot-v3/northbridge/intel/i945/raminit.c
===================================================================
--- coreboot-v3/northbridge/intel/i945/raminit.c 2009-01-08 15:44:56 UTC (rev 1105)
+++ coreboot-v3/northbridge/intel/i945/raminit.c 2009-01-08 16:01:25 UTC (rev 1106)
@@ -1158,7 +1158,7 @@
static int i945_silicon_revision(void)
{
- return pci_conf1_read_config8(PCI_BDF(0, 0x00, 0), 8);
+ return pci_conf1_read_config8(PCI_BDF(0, 0x00, 0), PCI_CLASS_REVISION);
}
static void sdram_force_rcomp(void)
@@ -1435,11 +1435,15 @@
tolud = (cum0 + cum1) << 1;
else
tolud = (cum1 ? cum1 : cum0) << 1;
- pci_conf1_write_config16(PCI_BDF(0,0,0), TOLUD, tolud);
-
+
+ /* Some extra checks needed. See 4.1.26 in the
+ * 82945G MCH datasheet (30750203)
+ */
+ pci_conf1_write_config8(PCI_BDF(0,0,0), TOLUD, tolud);
+
printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
- printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", tolud);
+ printk(BIOS_DEBUG, "TOLUD = 0x%02x\n", tolud);
pci_conf1_write_config16(PCI_BDF(0,0,0), TOM, tolud>>3);
@@ -2837,8 +2841,6 @@
pci_conf1_write_config8(PCI_BDF(0, 0x00, 0), PAM5, 0x33);
pci_conf1_write_config8(PCI_BDF(0, 0x00, 0), PAM6, 0x33);
- pci_conf1_write_config8(PCI_BDF(0, 0x00, 0), TOLUD, 0x40); /* 1G XXX dynamic! */
-
pci_conf1_write_config32(PCI_BDF(0, 0x00, 0), SKPAD, 0xcafebabe);
printk(BIOS_DEBUG, " done.\n");
@@ -3141,24 +3143,23 @@
u32 timeout;
u32 reg32;
u16 reg16;
- u8 reg8;
/* For now we just disable the x16 link */
printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n");
MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
- reg8 = pcie_read_config8(PCI_BDF(0, 0x01, 0), BCTRL1);
- reg8 |= (1 << 6);
- pcie_write_config8(PCI_BDF(0, 0x01, 0), BCTRL1, reg8);
+ reg16 = pcie_read_config16(PCI_BDF(0, 0x01, 0), BCTRL1);
+ reg16 |= (1 << 6);
+ pcie_write_config16(PCI_BDF(0, 0x01, 0), BCTRL1, reg16);
reg32 = pcie_read_config32(PCI_BDF(0, 0x01, 0), 0x224);
reg32 |= (1 << 8);
pcie_write_config32(PCI_BDF(0, 0x01, 0), 0x224, reg32);
- reg8 = pcie_read_config8(PCI_BDF(0, 0x01, 0), BCTRL1);
- reg8 &= ~(1 << 6);
- pcie_write_config8(PCI_BDF(0, 0x01, 0), BCTRL1, reg8);
+ reg16 = pcie_read_config16(PCI_BDF(0, 0x01, 0), BCTRL1);
+ reg16 &= ~(1 << 6);
+ pcie_write_config16(PCI_BDF(0, 0x01, 0), BCTRL1, reg16);
printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
timeout = 0x7fffff;
Modified: coreboot-v3/northbridge/intel/i945/rcven.c
===================================================================
--- coreboot-v3/northbridge/intel/i945/rcven.c 2009-01-08 15:44:56 UTC (rev 1105)
+++ coreboot-v3/northbridge/intel/i945/rcven.c 2009-01-08 16:01:25 UTC (rev 1106)
@@ -82,7 +82,7 @@
{
u32 reg32;
- printk(BIOS_SPEW, " set_receive_enable() medium=0x%x, coarse=0x%x\r\n", medium, coarse);
+ printk(BIOS_SPEW, " set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse);
reg32 = MCHBAR32(C0DRT1 + channel_offset);
reg32 &= 0xf0ffffff;
@@ -116,7 +116,7 @@
static int normalize(int channel_offset, u8 * mediumcoarse, u8 * fine)
{
- printk(BIOS_SPEW, " normalize()\r\n");
+ printk(BIOS_SPEW, " normalize()\n");
if (*fine < 0x80)
return 0;
@@ -125,7 +125,7 @@
*mediumcoarse += 1;
if (*mediumcoarse >= 0x40) {
- printk(BIOS_DEBUG, "Normalize Error\r\n");
+ printk(BIOS_DEBUG, "Normalize Error\n");
return -1;
}
@@ -143,12 +143,12 @@
/* find start of the data phase */
u32 reg32;
- printk(BIOS_SPEW, " find_preamble()\r\n");
+ printk(BIOS_SPEW, " find_preamble()\n");
do {
if (*mediumcoarse < 4) {
- printk(BIOS_DEBUG, "No Preamble found.\r\n");
+ printk(BIOS_DEBUG, "No Preamble found.\n");
return -1;
}
*mediumcoarse -= 4;
@@ -162,7 +162,7 @@
if (!(reg32 & (1 << 18))) {
- printk(BIOS_DEBUG, "No Preamble found (neither high nor low).\r\n");
+ printk(BIOS_DEBUG, "No Preamble found (neither high nor low).\n");
return -1;
}
@@ -175,14 +175,14 @@
static int add_quarter_clock(int channel_offset, u8 * mediumcoarse, u8 * fine)
{
- printk(BIOS_SPEW, " add_quarter_clock() mediumcoarse=%02x fine=%02x\r\n",
+ printk(BIOS_SPEW, " add_quarter_clock() mediumcoarse=%02x fine=%02x\n",
*mediumcoarse, *fine);
if (*fine >= 0x80) {
*fine -= 0x80;
*mediumcoarse += 2;
if (*mediumcoarse >= 0x40) {
- printk(BIOS_DEBUG, "clocks at max.\r\n");
+ printk(BIOS_DEBUG, "clocks at max.\n");
return -1;
}
@@ -202,7 +202,7 @@
{
u32 rcvenmt;
- printk(BIOS_SPEW, " find_strobes_low()\r\n");
+ printk(BIOS_SPEW, " find_strobes_low()\n");
for (;;) {
MCHBAR8(C0WL0REOST + channel_offset) = *fine;
@@ -228,7 +228,7 @@
}
- printk(BIOS_DEBUG, "Could not find low strobe\r\n");
+ printk(BIOS_DEBUG, "Could not find low strobe\n");
return 0;
}
@@ -238,7 +238,7 @@
int counter;
u32 rcvenmt;
- printk(BIOS_SPEW, " find_strobes_edge()\r\n");
+ printk(BIOS_SPEW, " find_strobes_edge()\n");
counter = 8;
set_receive_enable(channel_offset, *mediumcoarse & 3,
@@ -273,7 +273,7 @@
continue;
}
- printk(BIOS_DEBUG, "could not find rising edge.\r\n");
+ printk(BIOS_DEBUG, "could not find rising edge.\n");
return -1;
}
@@ -302,7 +302,7 @@
u8 mediumcoarse;
u8 fine;
- printk(BIOS_SPEW, "receive_enable_autoconfig() for channel %d\r\n",
+ printk(BIOS_SPEW, "receive_enable_autoconfig() for channel %d\n",
channel_offset ? 1 : 0);
/* Set initial values */
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