[coreboot] [patch] Proposed patch for FIDVID question

[Marc Jones]

On Thu, Jan 8, 2009 at 11:27 AM, Dan Lykowski <engineerguy3737 at yahoo.com> wrote:
> Marc,
>
> I have narrowed the reset to the first
>   msr = rdmsr(0xc0010042);
> line in cache_as_ram.c.
> I assume the second would do the same thing if it ever made it there.
>
> Booting with the orig bios, linux reports
> ts ttp tm stc 100mhzsteps
> as the available power options. It is missing fid vid.
>
> Based on the lack of cpuinfo bits and the documentation the says the
> processor will do exactly what it is doing, I propose the included patch.
> I made the changes to pistachio and norwich also but they are untested.
>
> With this patch I make it here:
>
> coreboot-2.0.0 Wed Jan  7 17:09:38 PST 2009
> starting...
> bsp_apicid=0x0
> Enabling routing table for node 00
> done.
> Enabling UP
> settings
> Disabling read/write/fill probes for UP...
> done.
> coherent_ht_finalize
> done
> core0
> started:
> SBLink=00
> NC
> node|link=00
> rs690_early_setup()
> get_cpu_rev
> EAX=0x60fc2.
> CPU Rev is
> K8_G0.
> NB Revision is
> A12.
> k8_optimization()
> rs690_por_init
> sb600_early_setup()
> sb600_devices_por_init()
> sb600_devices_por_init(): SMBus Device,
> BDF:0-20-0
> SMBus controller enabled, sb revision is
> 0x13
> sb600_devices_por_init(): IDE Device,
> BDF:0-20-1
> sb600_devices_por_init(): LPC Device,
> BDF:0-20-3
> sb600_devices_por_init(): P2P Bridge,
> BDF:0-20-4
> sb600_devices_por_init(): SATA Device,
> BDF:0-18-0
> sb600_pmio_por_init()
> Changing FIDVID not supported
>
> entering
> optimize_link_incoherent_ht
> sysinfo->link_pair_num=0x1
> entering
> ht_optimize_link
> pos=0x8a, unfiltered
> freq_cap=0x8035
> pos=0x8a, filtered
> freq_cap=0x35
> pos=0xd2, unfiltered
> freq_cap=0x65
> pos=0xd2, filtered
> freq_cap=0x65
> freq_cap1=0x35,
> freq_cap2=0x65
> dev1 old_freq=0x5, freq=0x5,
> needs_reset=0x0
> dev2 old_freq=0x5, freq=0x5,
> needs_reset=0x0
> width_cap1=0x11,
> width_cap2=0x11
> dev1 input ln_width1=0x4,
> ln_width2=0x4
> dev1 input
> width=0x1
> dev1 output ln_width1=0x4,
> ln_width2=0x4
> dev1 input|output
> width=0x11
> old dev1 input|output
> width=0x11
> dev2 input|output
> width=0x11
> old dev2 input|output
> width=0x11
> after ht_optimize_link for link pair 0,
> reset_needed=0x0
> after optimize_link_read_pointers_chain,
> reset_needed=0x0
> rs690_htinit
> k8_ht_freq=5.
> rs690_htinit
> NB_CFG_Q_F1000_800=0
> needs_reset=0x0
> sysinfo->nodes:  1  sysinfo->ctrl: cf188  spd_addr:
> ffffae98
> Ram1.00
> setting up CPU00 northbridge
> registers
> done.
> Ram2.00
> Enable 64MuxMode &
> BurstLength32
> Unbuffered
> 333Mhz
> 333Mhz
>
> Thanks,
> Dan Lykowski
>
> Signed-off-by: Dan Lykowski <lykowdk at gmail.com>

That looks correct to me. Maybe Bao or someone cold test and ack it.

Marc