[coreboot] Bug in cache_as_ram.inc and cache_as_ram_post.c

Myles Watson mylesgw at gmail.com
Wed Jul 1 18:34:56 CEST 2009


On Fri, Nov 28, 2008 at 2:16 PM, Thomas Jourdan <tjourdan at neuf.fr> wrote:

> Hi guys
>
> I don't know how usefull is it but there is a bug in cache_as_ram.inc
> and cache_as_ram_post.c for the 6fx intel processors. The code disable /
> enable the prefetcher in IA32_MISC_ENABLES MSR register.


Rev 4391.  Sorry it took so long.

Thanks,
Myles
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20090701/20b50671/attachment.html>


More information about the coreboot mailing list